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/external/llvm/test/CodeGen/ARM/
Dinlineasm3.ll41 tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind
50 call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind
58 call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
67 ; CHECK: flds s15, s0
68 %0 = tail call float asm "flds s15, $0", "=x"() nounwind
77 ; CHECK: flds s15, d0
78 %0 = tail call double asm "flds s15, $0", "=x"() nounwind
87 ; CHECK: flds s15, s0
88 %0 = tail call float asm "flds s15, $0", "=t"() nounwind
/external/compiler-rt/lib/arm/
Dfloatunssisfvfp.S22 vmov s15, r0 // move int to float register s15
23 vcvt.f32.u32 s15, s15 // convert 32-bit int in s15 to float in s15
24 vmov r0, s15 // move s15 to result register
Dfixsfsivfp.S22 vmov s15, r0 // load float register from R0
23 vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15
24 vmov r0, s15 // move s15 to result register
Dfloatsisfvfp.S22 vmov s15, r0 // move int to float register s15
23 vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15
24 vmov r0, s15 // move s15 to result register
Dfixunssfsivfp.S23 vmov s15, r0 // load float register from R0
24 vcvt.u32.f32 s15, s15 // convert single to 32-bit unsigned into s15
25 vmov r0, s15 // move s15 to result register
Dfloatunssidfvfp.S22 vmov s15, r0 // move int to float register s15
23 vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
Dtruncdfsf2vfp.S23 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
24 vmov r0, s15 // return result in r0
Dextendsfdf2vfp.S22 vmov s15, r0 // load float register from R0
23 vcvt.f64.f32 d7, s15 // convert single to double
Dfixdfsivfp.S23 vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
24 vmov r0, s15 // move s15 to result register
Dfloatsidfvfp.S22 vmov s15, r0 // move int to float register s15
23 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
Dfixunsdfsivfp.S24 vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
25 vmov r0, s15 // move s15 to result register
Dsubsf3vfp.S23 vmov s15, r1 // move second param from r1 into float register
24 vsub.f32 s14, s14, s15
Dmulsf3vfp.S22 vmov s15, r1 // move second param from r1 into float register
23 vmul.f32 s13, s14, s15
Daddsf3vfp.S22 vmov s15, r1 // move second param from r1 into float register
23 vadd.f32 s14, s14, s15
Ddivsf3vfp.S22 vmov s15, r1 // move second param from r1 into float register
23 vdiv.f32 s13, s14, s15
Dltsf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
Dnesf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
Dgesf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
Dunordsf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
Dlesf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
Dgtsf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
Deqsf2vfp.S23 vmov s15, r1 // move from GPR 1 to float register
24 vcmp.f32 s14, s15
/external/valgrind/main/none/tests/arm/
Dvfp.c1156 TESTINSN_bin_f32("vmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); in main()
1157 TESTINSN_bin_f32("vmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); in main()
1162 …TESTINSN_bin_f32("vmla.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)… in main()
1165 TESTINSN_bin_f32("vmla.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); in main()
1175 TESTINSN_bin_f32("vmla.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); in main()
1176 TESTINSN_bin_f32("vmla.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); in main()
1206 TESTINSN_bin_f32("vnmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); in main()
1207 TESTINSN_bin_f32("vnmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); in main()
1212 …TESTINSN_bin_f32("vnmla.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76… in main()
1215 TESTINSN_bin_f32("vnmla.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); in main()
[all …]
Dvfp.stdout.exp145 vmla.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
146 vmla.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
164 vmla.f32 s20, s13, s15 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
165 vmla.f32 s10, s23, s15 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
194 vnmla.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
195 vnmla.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
213 vnmla.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
214 vnmla.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
243 vmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
244 vmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
[all …]
/external/v8/benchmarks/
Dregexp.js108 var s15 = computeInputVariants(str0, 139);
163 /JroXvg\/(\S+)/.exec(s15[i]);
258 /Fnsnev\/(\d+\.\d+)/.exec(s15[i]);
287 …Cnenqvfb|Vprjrnfry).(\d+\.\d+))|(?:Bcren.(\d+\.\d+))|(?:NccyrJroXvg.(\d+(?:\.\d+)?))/.exec(s15[i]);
288 /(Znp BF K)|(Jvaqbjf;)/.exec(s15[i]);
289 /Trpxb\/([0-9]+)/.exec(s15[i]);
352 /puebzr/i.exec(s15[i]);
459 s15[i].match(/zfvr/gi);
460 s15[i].match(/bcren/gi);
543 /sversbk/i.exec(s15[i]);
[all …]

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