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/external/llvm/test/CodeGen/X86/
Dapm.ll1 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 | FileCheck %s
2 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefix=WIN64
16 tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
20 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
31 tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
35 declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
Dsse_reload_fold.ll1 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates -regalloc=b…
18 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
19 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)
20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
25 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
26 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>)
27 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
71 %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f)
76 %t = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %y, <4 x float> %f)
81 %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)
[all …]
Dfabs.ll2 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse2,-sse3,-sse | FileCheck %s
3 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-n…
Dsincos.ll2 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | FileCh…
3 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | FileCh…
D2009-02-26-MachineLICMBug.ll1 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats 2>&1 | grep "5 machine-licm"
2 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn | FileCheck %s
Dnegative_zero.ll1 ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | grep fchs
Dfp-immediate-shorten.ll3 ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | \
D2008-10-06-x87ld-nan-1.ll4 ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fldl
D2008-10-06-x87ld-nan-2.ll4 ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fldt | count 3
Dvec_compare-sse4.ll1 ; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2
Dvec_splat.ll2 ; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse3 | grep movddup
Dsibcall-5.ll3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-sse3 | FileCheck %s --check-prefix=X64_BAD
D2009-04-21-NoReloadImpDef.ll2 ; RUN: -mcpu=generic -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false -regal…
Davx-intrinsics-x86.ll761 …%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x doub…
764 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
769 …%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>>…
772 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
777 …%res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
780 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
785 …%res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […
788 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
793 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
796 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
[all …]
Dhaddsub.ll1 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
2 ; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
/external/flac/libFLAC/
Dcpu.c171 info->data.ia32.sse3 = false; in FLAC__cpu_info()
185 info->data.ia32.sse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE3 )? true : false; in FLAC__cpu_info()
206 fprintf(stderr, " SSE3 ....... %c\n", info->data.ia32.sse3 ? 'Y' : 'n'); in FLAC__cpu_info()
219 …info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->d… in FLAC__cpu_info()
229 …info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->d… in FLAC__cpu_info()
235 …info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->d… in FLAC__cpu_info()
240 info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false; in FLAC__cpu_info()
243 …info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->d… in FLAC__cpu_info()
282 …info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->d… in FLAC__cpu_info()
299 …info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->d… in FLAC__cpu_info()
[all …]
/external/libvpx/vp8/encoder/x86/
Dvariance_mmx.c97 unsigned int sse0, sse1, sse2, sse3, var; in vp8_get16x16var_mmx() local
104 … 8 * source_stride + 8, source_stride, ref_ptr + 8 * recon_stride + 8, recon_stride, &sse3, &sum3); in vp8_get16x16var_mmx()
106 var = sse0 + sse1 + sse2 + sse3; in vp8_get16x16var_mmx()
159 unsigned int sse0, sse1, sse2, sse3, var; in vp8_mse16x16_mmx() local
166 … 8 * source_stride + 8, source_stride, ref_ptr + 8 * recon_stride + 8, recon_stride, &sse3, &sum3); in vp8_mse16x16_mmx()
168 var = sse0 + sse1 + sse2 + sse3; in vp8_mse16x16_mmx()
181 unsigned int sse0, sse1, sse2, sse3, var; in vp8_variance16x16_mmx() local
188 … 8 * source_stride + 8, source_stride, ref_ptr + 8 * recon_stride + 8, recon_stride, &sse3, &sum3); in vp8_variance16x16_mmx()
190 var = sse0 + sse1 + sse2 + sse3; in vp8_variance16x16_mmx()
/external/clang/lib/Headers/
Dmodule.map41 explicit module sse3 {
42 requires sse3
49 export sse3
89 export sse3
/external/valgrind/main/docs/internals/
D3_1_BUGSTATUS.txt58 low 126257 vex x86->IR: 0xF2 0x0F 0xF0 0x40 (lddqu) (sse3)
59 low 126258 vex x86->IR: 0xDF 0x4D (fisttp) (sse3)
62 126400 addsubpd (sse3)
63 126417 haddpd (sse3)
64 126418 haddps (sse3)
65 126419 hsubps (sse3)
66 126420 hsubpd (sse3)
67 126421 movddup (sse3)
/external/valgrind/main/none/tests/x86/
Dinsn_sse3.vgtest2 prereq: ../../../tests/x86_amd64_features x86-sse3
/external/valgrind/main/none/tests/amd64/
Dinsn_sse3.vgtest2 prereq: ../../../tests/x86_amd64_features amd64-sse3
/external/flac/libFLAC/include/private/
Dcpu.h55 FLAC__bool sse3; member
/external/llvm/lib/Target/X86/
DX86.td47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
213 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
215 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
217 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
/external/eigen/Eigen/
DCore63 // Detect sse3/ssse3/sse4:
/external/libvpx/build/make/
Dconfigure.sh847 soft_enable sse3

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