Searched refs:vvvv (Results 1 – 6 of 6) sorted by relevance
3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
1284 insn->vvvv = (Reg)fixupRegValue(insn, in fixupReg()1286 insn->vvvv, in fixupReg()1466 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]); in readVVVV()1468 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]); in readVVVV()1473 insn->vvvv &= 0x7; in readVVVV()1495 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands()
498 Reg vvvv; member
764 translateRegister(mcInst, insn.vvvv); in translateOperand()
326 was more like 100:1. You can use the -vvvv option to mon-
329 was more like 100:1. You can use the −vvvv option to mon