1 /* 2 * public_host_int.h 3 * 4 * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /********************************************************************************************************************** 35 36 FILENAME: public_host_int.h 37 38 DESCRIPTION: Contains the host interface fw interrupt structure in use. 39 40 41 42 ***********************************************************************************************************************/ 43 #ifndef PUBLIC_HOST_INT_H 44 #define PUBLIC_HOST_INT_H 45 46 #include "public_types.h" 47 48 49 /************************************************************************* 50 51 Host Interrupt Register (WiLink -> Host) 52 53 **************************************************************************/ 54 #define ACX_INTR_WATCHDOG BIT_0 /* HW Initiated interrupt Watchdog timer expiration */ 55 #define ACX_INTR_INIT_COMPLETE BIT_1 /* Init sequence is done (masked interrupt, detection through polling only ) */ 56 #define ACX_INTR_EVENT_A BIT_2 /* Event was entered to Event MBOX #A*/ 57 #define ACX_INTR_EVENT_B BIT_3 /* Event was entered to Event MBOX #B*/ 58 #define ACX_INTR_CMD_COMPLETE BIT_4 /* Command processing completion*/ 59 #define ACX_INTR_HW_AVAILABLE BIT_5 /* Signaling the host on HW wakeup */ 60 #define ACX_INTR_DATA BIT_6 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ 61 #define ACX_INTR_TRACE_A BIT_7 /* Trace meassge on MBOX #A */ 62 #define ACX_INTR_TRACE_B BIT_8 /* Trace meassge on MBOX #B */ 63 64 #define ACX_INTR_ALL 0xFFFFFFFF 65 66 67 /************************************************************************* 68 69 Interrupt Trigger Register (Host -> WiLink) 70 71 **************************************************************************/ 72 73 /******** Hardware to Embedded CPU Interrupts - first 32-bit register set ********/ 74 75 #define INTR_TRIG_CMD BIT_0 /* Host Command Interrupt. Setting this bit masks*/ 76 /* the interrupt that the host issues to inform*/ 77 /* the FW that it has sent a command*/ 78 /* to the Wlan hardware Command Mailbox.*/ 79 80 #define INTR_TRIG_EVENT_ACK BIT_1 /* Host Event Acknowlegde Interrupt. The host */ 81 /* sets this bit to acknowledge that it received*/ 82 /* the unsolicited information from the event*/ 83 /* mailbox.*/ 84 85 #define INTR_TRIG_TX_PROC0 BIT_2 /* OBSOLETE (automatic end-of-transaction interrupt is used instead) */ 86 87 #define INTR_TRIG_RX_PROC BIT_3 /* The host sets this bit to inform the FW that */ 88 /* it read a packet from the RX cyclic buffer */ 89 90 #define INTR_TRIG_DEBUG_ACK BIT_4 91 92 #define INTR_TRIG_STATE_CHANGED BIT_5 93 94 95 /******** Hardware to Embedded CPU Interrupts - second 32-bit register set ********/ 96 97 #define INTR_TRIG_RX_PROC1 BIT_17 /* OBSOLETE */ 98 99 #define INTR_TRIG_TX_PROC1 BIT_18 /* OBSOLETE */ 100 101 102 /************************************************************************* 103 104 FW status registers (Host reads from FW upon interrupt from FW) 105 106 **************************************************************************/ 107 #define NUM_TX_QUEUES 4 /* Number of Tx HW Queues (same as ACs). */ 108 #define NUM_RX_PKT_DESC 8 /* Number of Rx packets short descriptors in the W status */ 109 110 /* Get field from FwStatus_t->rxPktsDesc[i] */ 111 #define RX_DESC_GET_MEM_BLK(desc) ( (desc & 0x000000FF) >> 0 ) /* The first mem-block of the Rx packet */ 112 #define RX_DESC_GET_LENGTH(desc) ( (desc & 0x000FFF00) >> 8 ) /* The length of the packet in words */ 113 #define RX_DESC_GET_UNALIGNED(desc) ( (desc & 0x00100000) >> 20 ) /* If set, the payload is not 4 bytes aligned */ 114 #define RX_DESC_GET_PACKET_CLASS_TAG(desc) ( (desc & 0xFF000000) >> 24 ) /* Get the RX packet class tag */ 115 116 117 /* Set field in FwStatus_t->rxPktsDesc[i] */ 118 #define RX_DESC_SET_MEM_BLK(desc, value) ( desc = (desc & ~0x000000FF) | (value << 0 ) ) 119 #define RX_DESC_SET_LENGTH(desc, value) ( desc = (desc & ~0x000FFF00) | (value << 8 ) ) 120 #define RX_DESC_SET_UNALIGNED(desc, value) ( desc = (desc & ~0x00100000) | (value << 20 ) ) 121 122 /* The content of the "counters" field in FwStatus_t - see below */ 123 typedef struct 124 { 125 uint8 fwRxCntr; /* Incremented by FW upon adding pending Rx entry to aRxPktsDesc */ 126 uint8 drvRxCntr; /* Incremented by FW upon RX host slave interrupt (for debug) */ 127 uint8 reserved; 128 uint8 txResultsCntr; /* Incremented by FW upon adding Tx-Result to the TxResultQueue */ 129 } FwStatCntrs_t; 130 131 /* The FW status registers structure read by the host upon interrupt from the FW */ 132 typedef struct 133 { 134 uint32 intrStatus; /* HINT register content (will be cleared upon the read) */ 135 uint32 counters; /* The counters defined in FwStatCntrs_t - see above */ 136 uint32 rxPktsDesc[NUM_RX_PKT_DESC]; /* Array of Rx packets short descriptors (see RX_DESC_SET/GET...) */ 137 uint32 txReleasedBlks[NUM_TX_QUEUES]; /* Per queue released blocks count since FW-reset */ 138 uint32 fwLocalTime; /* FW time in usec, used for clock synchronization with the host */ 139 uint32 spare[2]; /* Total structure size is 68 bytes */ 140 } FwStatus_t; 141 142 #endif 143 144 145