1 /* 2 * Device1273.h 3 * 4 * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /********************************************************************************************************************** 36 37 FILENAME: Device1273.h 38 39 DESCRIPTION: TNETW1273 Registes addresses/defintion 40 41 42 43 ***********************************************************************************************************************/ 44 45 #ifndef DEVICE1273_H 46 #define DEVICE1273_H 47 48 49 /* Base addresses*/ 50 /* They are not used inside registers definition in purpose to allow this header file*/ 51 /* to be used as an easy reference to register -> address date base. Keep this as it*/ 52 /* is very powerful for debugging purpose.*/ 53 #define REGISTERS_BASE 0x00300000 54 #define INT_BASE 0x00300400 55 #define REG_CONFIG_BASE 0x00300800 56 #define CLK_BASE 0x00300C00 57 #define SDMA_BASE 0x00301000 58 #define AES_BASE 0x00301400 59 #define WEP_BASE 0x00301800 60 #define TKIP_BASE 0x00301C00 61 #define SEEPROM_BASE 0x00302000 62 #define PAR_HOST_BASE 0x00302400 63 #define SDIO_BASE 0x00302800 64 #define UART_BASE 0x00302C00 65 #define USB11_BASE 0x00304000 66 #define LDMA_BASE 0x00304400 67 #define RX_BASE 0x00304800 68 #define ACCESS_BASE 0x00304c00 69 #define TX_BASE 0x00305000 70 #define RMAC_CSR_BASE 0x00305400 71 #define AFE_PM 0x00305800 72 #define VLYNQ_BASE 0x00308000 73 #define PCI_BASE 0x00308400 74 #define USB20_BASE 0x0030A000 75 #define DRPW_BASE 0x00310000 76 #define PHY_BASE 0x003C0000 77 78 /* DRPw init scratch register */ 79 #define DRPW_SCRATCH_START (DRPW_BASE + 0x002C) 80 81 /* System DMA registers*/ 82 /* Order of registers was changed*/ 83 #define DMA_GLB_CFG (REGISTERS_BASE + 0x1000) 84 #define DMA_HDESC_OFFSET (REGISTERS_BASE + 0x1004) 85 #define DMA_HDATA_OFFSET (REGISTERS_BASE + 0x1008) 86 #define DMA_CFG0 (REGISTERS_BASE + 0x100C) /* SDMA_HOST_CFG0 changed*/ 87 #define DMA_CTL0 (REGISTERS_BASE + 0x1010) /* SDMA_CTRL0 changed*/ 88 #define DMA_LENGTH0 (REGISTERS_BASE + 0x1014) 89 #define DMA_L_ADDR0 (REGISTERS_BASE + 0x1018) /* SDMA_RD_ADDR ?*/ 90 #define DMA_L_PTR0 (REGISTERS_BASE + 0x101C) /* SDMA_RD_OFFSET ?*/ 91 #define DMA_H_ADDR0 (REGISTERS_BASE + 0x1020) /* SDMA_WR_ADDR ?*/ 92 #define DMA_H_PTR0 (REGISTERS_BASE + 0x1024) /* SDMA_WR_OFFSET ?*/ 93 #define DMA_STS0 (REGISTERS_BASE + 0x1028) /* Changed*/ 94 #define DMA_CFG1 (REGISTERS_BASE + 0x1030) /* SDMA_HOST_CFG1 changed*/ 95 #define DMA_CTL1 (REGISTERS_BASE + 0x1034) /* SDMA_CTRL1 changed*/ 96 #define DMA_LENGTH1 (REGISTERS_BASE + 0x1038) 97 #define DMA_L_ADDR1 (REGISTERS_BASE + 0x103C) 98 #define DMA_L_PTR1 (REGISTERS_BASE + 0x1040) 99 #define DMA_H_ADDR1 (REGISTERS_BASE + 0x1044) 100 #define DMA_H_PTR1 (REGISTERS_BASE + 0x1048) 101 #define DMA_STS1 (REGISTERS_BASE + 0x104C) 102 #define DMA_HFRM_PTR (REGISTERS_BASE + 0x1050) /* New ?*/ 103 #define DMA_DEBUG (REGISTERS_BASE + 0x1054) /* Changed*/ 104 105 /* Local DMA registers*/ 106 /* number changed from 4 to 2*/ 107 #define LDMA_DEBUG (REGISTERS_BASE + 0x4400) 108 #define LDMA_CTL0 (REGISTERS_BASE + 0x4404) /* Add 2 bits to support fix address (FIFO)*/ 109 #define LDMA_STATUS0 (REGISTERS_BASE + 0x4408) 110 #define LDMA_LENGTH0 (REGISTERS_BASE + 0x440c) 111 #define LDMA_RD_ADDR0 (REGISTERS_BASE + 0x4410) 112 #define LDMA_RD_OFFSET0 (REGISTERS_BASE + 0x4414) 113 #define LDMA_WR_ADDR0 (REGISTERS_BASE + 0x4418) 114 #define LDMA_WR_OFFSET0 (REGISTERS_BASE + 0x441c) 115 #define LDMA_CTL1 (REGISTERS_BASE + 0x4428) /* Add 2 bits to support fix address (FIFO)*/ 116 #define LDMA_STATUS1 (REGISTERS_BASE + 0x442c) 117 #define LDMA_LENGTH1 (REGISTERS_BASE + 0x4430) 118 #define LDMA_RD_ADDR1 (REGISTERS_BASE + 0x4434) 119 #define LDMA_RD_OFFSET1 (REGISTERS_BASE + 0x4438) 120 #define LDMA_WR_ADDR1 (REGISTERS_BASE + 0x443c) 121 #define LDMA_WR_OFFSET1 (REGISTERS_BASE + 0x4440) 122 /* For TNETW compatability (if willbe )*/ 123 #define LDMA_CUR_RD_PTR0 LDMA_RD_ADDR0 124 #define LDMA_CUR_WR_PTR0 LDMA_WR_ADDR0 125 #define LDMA_CUR_RD_PTR1 LDMA_RD_ADDR1 126 #define LDMA_CUR_WR_PTR1 LDMA_WR_ADDR1 127 128 /* Host Slave registers*/ 129 #define SLV_SOFT_RESET (REGISTERS_BASE + 0x0000) /* self clearing*/ 130 #define SLV_REG_ADDR (REGISTERS_BASE + 0x0004) 131 #define SLV_REG_DATA (REGISTERS_BASE + 0x0008) 132 #define SLV_REG_ADATA (REGISTERS_BASE + 0x000c) 133 #define SLV_MEM_CP (REGISTERS_BASE + 0x0010) 134 #define SLV_MEM_ADDR (REGISTERS_BASE + 0x0014) 135 #define SLV_MEM_DATA (REGISTERS_BASE + 0x0018) 136 #define SLV_MEM_CTL (REGISTERS_BASE + 0x001c) /* bit 19 moved to PCMCIA_CTL*/ 137 #define SLV_END_CTL (REGISTERS_BASE + 0x0020) /* 2 bits moved to ENDIAN_CTL*/ 138 139 /* Timer registers*/ 140 /* Timer1/2 count MAC clocks*/ 141 /* Timer3/4/5 count usec*/ 142 #define TIM1_CTRL (REGISTERS_BASE + 0x0918) 143 #define TIM1_LOAD (REGISTERS_BASE + 0x091C) 144 #define TIM1_CNT (REGISTERS_BASE + 0x0920) 145 #define TIM2_CTRL (REGISTERS_BASE + 0x0924) 146 #define TIM2_LOAD (REGISTERS_BASE + 0x0928) 147 #define TIM2_CNT (REGISTERS_BASE + 0x092C) 148 #define TIM3_CTRL (REGISTERS_BASE + 0x0930) 149 #define TIM3_LOAD (REGISTERS_BASE + 0x0934) 150 #define TIM3_CNT (REGISTERS_BASE + 0x0938) 151 #define TIM4_CTRL (REGISTERS_BASE + 0x093C) 152 #define TIM4_LOAD (REGISTERS_BASE + 0x0940) 153 #define TIM4_CNT (REGISTERS_BASE + 0x0944) 154 #define TIM5_CTRL (REGISTERS_BASE + 0x0948) 155 #define TIM5_LOAD (REGISTERS_BASE + 0x094C) 156 #define TIM5_CNT (REGISTERS_BASE + 0x0950) 157 158 /* Watchdog registers*/ 159 #define WDOG_CTRL (REGISTERS_BASE + 0x0954) 160 #define WDOG_LOAD (REGISTERS_BASE + 0x0958) 161 #define WDOG_CNT (REGISTERS_BASE + 0x095C) 162 #define WDOG_STS (REGISTERS_BASE + 0x0960) 163 #define WDOG_FEED (REGISTERS_BASE + 0x0964) 164 165 /* Interrupt registers*/ 166 /* 64 bit interrupt sources registers ws ced. sme interupts were removed and new ones were added*/ 167 /* Order was changed*/ 168 #define FIQ_MASK (REGISTERS_BASE + 0x0400) 169 #define FIQ_MASK_L (REGISTERS_BASE + 0x0400) 170 #define FIQ_MASK_H (REGISTERS_BASE + 0x0404) 171 #define FIQ_MASK_SET (REGISTERS_BASE + 0x0408) 172 #define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408) 173 #define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C) 174 #define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410) 175 #define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410) 176 #define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414) 177 #define IRQ_MASK (REGISTERS_BASE + 0x0418) 178 #define IRQ_MASK_L (REGISTERS_BASE + 0x0418) 179 #define IRQ_MASK_H (REGISTERS_BASE + 0x041C) 180 #define IRQ_MASK_SET (REGISTERS_BASE + 0x0420) 181 #define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420) 182 #define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424) 183 #define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428) 184 #define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428) 185 #define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C) 186 #define ECPU_MASK (REGISTERS_BASE + 0x0448) 187 #define FIQ_STS_L (REGISTERS_BASE + 0x044C) 188 #define FIQ_STS_H (REGISTERS_BASE + 0x0450) 189 #define IRQ_STS_L (REGISTERS_BASE + 0x0454) 190 #define IRQ_STS_H (REGISTERS_BASE + 0x0458) 191 #define INT_STS_ND (REGISTERS_BASE + 0x0464) 192 #define INT_STS_RAW_L (REGISTERS_BASE + 0x0464) 193 #define INT_STS_RAW_H (REGISTERS_BASE + 0x0468) 194 #define INT_STS_CLR (REGISTERS_BASE + 0x04B4) 195 #define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4) 196 #define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8) 197 #define INT_ACK (REGISTERS_BASE + 0x046C) 198 #define INT_ACK_L (REGISTERS_BASE + 0x046C) 199 #define INT_ACK_H (REGISTERS_BASE + 0x0470) 200 #define INT_TRIG (REGISTERS_BASE + 0x0474) 201 #define INT_TRIG_L (REGISTERS_BASE + 0x0474) 202 #define INT_TRIG_H (REGISTERS_BASE + 0x0478) 203 #define HOST_STS_L (REGISTERS_BASE + 0x045C) 204 #define HOST_STS_H (REGISTERS_BASE + 0x0460) 205 #define HOST_MASK (REGISTERS_BASE + 0x0430) 206 #define HOST_MASK_L (REGISTERS_BASE + 0x0430) 207 #define HOST_MASK_H (REGISTERS_BASE + 0x0434) 208 #define HOST_MASK_SET (REGISTERS_BASE + 0x0438) 209 #define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438) 210 #define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C) 211 #define HOST_MASK_CLR (REGISTERS_BASE + 0x0440) 212 #define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440) 213 #define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444) 214 215 /* GPIO Interrupts*/ 216 #define GPIO_INT_STS (REGISTERS_BASE + 0x0484) /* 22 GPIOs*/ 217 #define GPIO_INT_ACK (REGISTERS_BASE + 0x047C) 218 #define GPIO_INT_MASK (REGISTERS_BASE + 0x0480) 219 #define GPIO_POS_MASK (REGISTERS_BASE + 0x04BC) /* New*/ 220 #define GPIO_NEG_MASK (REGISTERS_BASE + 0x04C0) /* New*/ 221 222 /* Protocol Interrupts*/ 223 #define PROTO_INT_STS (REGISTERS_BASE + 0x0490) /* Add 2 PHY->MAC source interrupts*/ 224 #define PROTO_INT_ACK (REGISTERS_BASE + 0x0488) 225 #define PROTO_INT_MASK (REGISTERS_BASE + 0x048C) 226 227 /* Host Interrupts - The following Addresses are for 1273 */ 228 #define HINT_MASK (REGISTERS_BASE + 0x04DC) 229 #define HINT_MASK_SET (REGISTERS_BASE + 0x04E0) 230 #define HINT_MASK_CLR (REGISTERS_BASE + 0x04E4) 231 #define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04EC) 232 #define HINT_STS_ND (REGISTERS_BASE + 0x04E8) /* 1150 spec calls this HINT_STS_RAW*/ 233 #define HINT_STS_CLR (REGISTERS_BASE + 0x04F8) 234 #define HINT_ACK (REGISTERS_BASE + 0x04F0) 235 #define HINT_TRIG (REGISTERS_BASE + 0x04F4) 236 237 /* Clock registers*/ 238 #define CLK_CFG (REGISTERS_BASE + 0x0C00) /* new ARM clock bit */ 239 #define CLK_CTRL (REGISTERS_BASE + 0x0C04) /* changed*/ 240 #define BLK_RST (REGISTERS_BASE + 0x0C08) /* changed*/ 241 #define CFG_USEC_STB (REGISTERS_BASE + 0x0C0C) 242 #define ARM_GATE_CLK_REG (REGISTERS_BASE + 0x0C10) /* new*/ 243 #define BUSY_STAT_REG (REGISTERS_BASE + 0x0C14) /* new*/ 244 #define CFG_PHY_CLK88 (REGISTERS_BASE + 0x0C18) 245 #define DYNAMIC_CLKGATE (REGISTERS_BASE + 0x0C1C) /* new*/ 246 247 /* AES registers*/ 248 /* Major changes to this module*/ 249 #define AES_START (REGISTERS_BASE + 0x1400) 250 #define AES_CFG (REGISTERS_BASE + 0x1404) 251 #define AES_CTL (REGISTERS_BASE + 0x1408) 252 #define AES_STATUS (REGISTERS_BASE + 0x140C) 253 #define AES_LENGTH (REGISTERS_BASE + 0x1410) 254 #define AES_RD_ADDR (REGISTERS_BASE + 0x1414) 255 #define AES_RD_OFFSET (REGISTERS_BASE + 0x1418) 256 #define AES_WR_ADDR (REGISTERS_BASE + 0x141C) 257 #define AES_WR_OFFSET (REGISTERS_BASE + 0x1420) 258 #define AES_CUR_RD_PTR (REGISTERS_BASE + 0x1424) 259 #define AES_CUR_WR_PTR (REGISTERS_BASE + 0x1428) 260 #define AES_KEY_0 (REGISTERS_BASE + 0x142C) 261 #define AES_KEY_1 (REGISTERS_BASE + 0x1430) 262 #define AES_KEY_2 (REGISTERS_BASE + 0x1434) 263 #define AES_KEY_3 (REGISTERS_BASE + 0x1438) 264 #define AES_NONCE_0 (REGISTERS_BASE + 0x143C) 265 #define AES_NONCE_1 (REGISTERS_BASE + 0x1440) 266 #define AES_NONCE_2 (REGISTERS_BASE + 0x1444) 267 #define AES_NONCE_3 (REGISTERS_BASE + 0x1448) 268 #define AES_MIC_0 (REGISTERS_BASE + 0x144C) 269 #define AES_MIC_1 (REGISTERS_BASE + 0x1450) 270 #define AES_MIC_2 (REGISTERS_BASE + 0x1454) 271 #define AES_MIC_3 (REGISTERS_BASE + 0x1458) 272 #define AES_ASSO_DATA_0 (REGISTERS_BASE + 0x145C) 273 #define AES_ASSO_DATA_1 (REGISTERS_BASE + 0x1460) 274 #define AES_ASSO_DATA_2 (REGISTERS_BASE + 0x1464) 275 #define AES_ASSO_DATA_3 (REGISTERS_BASE + 0x1468) 276 #define AES_NUM_OF_ROUNDS (REGISTERS_BASE + 0x146C) 277 #define AES_TX_QUEUE_PTR (REGISTERS_BASE + 0x1470) 278 #define AES_RX_QUEUE_PTR (REGISTERS_BASE + 0x1474) 279 #define AES_STACK (REGISTERS_BASE + 0x1478) 280 #define AES_INT_RAW (REGISTERS_BASE + 0x147C) 281 #define AES_INT_MASK (REGISTERS_BASE + 0x1480) 282 #define AES_INT_STS (REGISTERS_BASE + 0x1484) 283 284 /* WEP registers*/ 285 /* Order was changed*/ 286 #define DEC_CTL (REGISTERS_BASE + 0x1800) 287 #define DEC_STATUS (REGISTERS_BASE + 0x1804) 288 #define DEC_MBLK (REGISTERS_BASE + 0x1808) 289 #define DEC_KEY_ADDR (REGISTERS_BASE + 0x180C) 290 #define DEC_KEY_LEN (REGISTERS_BASE + 0x1810) 291 #define DEC_ADDR_UPPER_BYTE (REGISTERS_BASE + 0x1814) /* new*/ 292 #define DEC_LEN (REGISTERS_BASE + 0x1818) 293 #define DEC_OFFSET (REGISTERS_BASE + 0x181C) 294 #define DEC_WR_MBLK (REGISTERS_BASE + 0x1820) 295 #define DEC_WR_OFFSET (REGISTERS_BASE + 0x1824) 296 297 /* TKIP MICHAEL reisters*/ 298 /* order changed*/ 299 #define MCHL_START0 (REGISTERS_BASE + 0x1C00) 300 #define MCHL_DMV_START_MBLK0 (REGISTERS_BASE + 0x1C04) /* Changed to 23:5 format*/ 301 #define MCHL_DMV_CUR_MBLK0 (REGISTERS_BASE + 0x1C10) 302 #define MCHL_DMV_OFFSET0 (REGISTERS_BASE + 0x1C08) 303 #define MCHL_DMV_LENGTH0 (REGISTERS_BASE + 0x1C0C) 304 #define MCHL_DMV_CFG0 (REGISTERS_BASE + 0x1C14) 305 #define MCHL_KEY_L0 (REGISTERS_BASE + 0x1C18) 306 #define MCHL_KEY_H0 (REGISTERS_BASE + 0x1C1C) 307 #define MCHL_MIC_L0 (REGISTERS_BASE + 0x1C20) 308 #define MCHL_MIC_H0 (REGISTERS_BASE + 0x1C24) 309 #define MCHL_START1 (REGISTERS_BASE + 0x1C28) 310 #define MCHL_DMV_START_MBLK1 (REGISTERS_BASE + 0x1C2C) /* Changed to 23:5 format*/ 311 #define MCHL_DMV_CUR_MBLK1 (REGISTERS_BASE + 0x1C38) 312 #define MCHL_DMV_OFFSET1 (REGISTERS_BASE + 0x1C30) 313 #define MCHL_DMV_LENGTH1 (REGISTERS_BASE + 0x1C34) 314 #define MCHL_DMV_CFG1 (REGISTERS_BASE + 0x1C3C) 315 #define MCHL_KEY_L1 (REGISTERS_BASE + 0x1C40) 316 #define MCHL_KEY_H1 (REGISTERS_BASE + 0x1C44) 317 #define MCHL_MIC_L1 (REGISTERS_BASE + 0x1C48) 318 #define MCHL_MIC_H1 (REGISTERS_BASE + 0x1C4C) 319 #define MCHL_CTL0 (REGISTERS_BASE + 0x1C50) /* new name MCHL_CTRL0*/ 320 #define MCHL_CTL1 (REGISTERS_BASE + 0x1C54) /* new name MCHL_CTRL1*/ 321 #define MCHL_UPPER_BYTE_ADDR0 (REGISTERS_BASE + 0x1C58) /* new*/ 322 #define MCHL_UPPER_BYTE_ADDR1 (REGISTERS_BASE + 0x1C5C) /* new*/ 323 324 /* SEEPROM registers*/ 325 #define EE_CFG (REGISTERS_BASE + 0x0820) 326 #define EE_CTL (REGISTERS_BASE + 0x2000) 327 #define EE_DATA (REGISTERS_BASE + 0x2004) 328 #define EE_ADDR (REGISTERS_BASE + 0x2008) 329 330 /* Parallel Host (PCI/CARDBUS/PCMCIA/GS*/ 331 #define CIS_LADDR (REGISTERS_BASE + 0x2400) 332 #define HI_CTL (REGISTERS_BASE + 0x2404) 333 #define LPWR_MGT (REGISTERS_BASE + 0x2408) 334 /*#define PDR0 (REGISTERS_BASE + 0x04ec)*/ 335 /*#define PDR1 (REGISTERS_BASE + 0x04f0)*/ 336 /*#define PDR2 (REGISTERS_BASE + 0x04f4)*/ 337 /*#define PDR3 (REGISTERS_BASE + 0x04f8)*/ 338 /*#define BAR2_ENABLE (REGISTERS_BASE + 0x04fc)*/ 339 /*#define BAR2_TRANS (REGISTERS_BASE + 0x0500)*/ 340 /*#define BAR2_MASK (REGISTERS_BASE + 0x0504)*/ 341 #define PCI_MEM_SIZE1 (REGISTERS_BASE + 0x2428) 342 #define PCI_MEM_OFFSET1 (REGISTERS_BASE + 0x242C) 343 #define PCI_MEM_OFFSET2 (REGISTERS_BASE + 0x2430) 344 /*#define PCI_IO_SIZE1 (REGISTERS_BASE + 0x0514)*/ 345 /*#define PCI_IO_OFFSET1 (REGISTERS_BASE + 0x0518)*/ 346 /*#define PCI_IO_OFFSET2 (REGISTERS_BASE + 0x051c)*/ 347 /*#define PCI_CFG_OFFSET (REGISTERS_BASE + 0x0520)*/ 348 #define PCMCIA_CFG (REGISTERS_BASE + 0x2444) 349 #define PCMCIA_CTL (REGISTERS_BASE + 0x2448) 350 #define PCMCIA_CFG2 (REGISTERS_BASE + 0x244C) /* new*/ 351 #define SRAM_PAGE (REGISTERS_BASE + 0x2450) 352 #define CFG_PULLUPDN (REGISTERS_BASE + 0x2454) 353 #define CIS_MAP (REGISTERS_BASE + 0x2458) /* new*/ 354 #define ENDIAN_CTRL (REGISTERS_BASE + 0x245C) /* new*/ 355 #define GS_SLEEP_ACCESS (REGISTERS_BASE + 0x2480) /* new*/ 356 #define PCMCIA_PWR_DN (REGISTERS_BASE + 0x04C4) 357 #define PCI_OUTPUT_DLY_CFG (REGISTERS_BASE + 0x2464) /* new*/ 358 359 /* VLYNQ registers*/ 360 /* VLYNQ2 was removed from hardware*/ 361 #define VL1_REV_ID (REGISTERS_BASE + 0x8000) /* VLYNQ_REVISION*/ 362 #define VL1_CTL (REGISTERS_BASE + 0x8004) /* VLYNQ_ CONTROL*/ 363 #define VL1_STS (REGISTERS_BASE + 0x8008) /* VLYNQ_STATUS*/ 364 #define VLYNQ_INTVEC (REGISTERS_BASE + 0x800C) 365 #define VL1_INT_STS (REGISTERS_BASE + 0x8010) /* VLYNQ_INTCR*/ 366 #define VL1_INT_PEND (REGISTERS_BASE + 0x8014) /* VLYNQ_INTSR*/ 367 #define VL1_INT_PTR (REGISTERS_BASE + 0x8018) /* VLYNQ_INTPTR*/ 368 #define VL1_TX_ADDR (REGISTERS_BASE + 0x801C) /* VLYNQ_TX_MAP_ADDR*/ 369 #define VL1_RX_SIZE1 (REGISTERS_BASE + 0x8020) /* VLYNQ_RX_MAP_SIZE1*/ 370 #define VL1_RX_OFF1 (REGISTERS_BASE + 0x8024) /* VLYNQ_RX_MAP_OFFSET1*/ 371 #define VL1_RX_SIZE2 (REGISTERS_BASE + 0x8028) /* VLYNQ_RX_MAP_SIZE2*/ 372 #define VL1_RX_OFF2 (REGISTERS_BASE + 0x802C) /* VLYNQ_RX_MAP_OFFSET2*/ 373 #define VL1_RX_SIZE3 (REGISTERS_BASE + 0x8030) /* VLYNQ_RX_MAP_SIZE3*/ 374 #define VL1_RX_OFF3 (REGISTERS_BASE + 0x8034) /* VLYNQ_RX_MAP_OFFSET3*/ 375 #define VL1_RX_SIZE4 (REGISTERS_BASE + 0x8038) /* VLYNQ_RX_MAP_SIZE4*/ 376 #define VL1_RX_OFF4 (REGISTERS_BASE + 0x803C) /* VLYNQ_RX_MAP_OFFSET4*/ 377 #define VL1_CHIP_VER (REGISTERS_BASE + 0x8040) /* VLYNQ_CHIP_VER*/ 378 #define VLYNQ_AUTONEG (REGISTERS_BASE + 0x8044) 379 #define VLYNQ_MANNEG (REGISTERS_BASE + 0x8048) 380 #define VLYNQ_NEGSTAT (REGISTERS_BASE + 0x804C) 381 #define VLYNQ_ENDIAN (REGISTERS_BASE + 0x805C) 382 #define VL1_INT_VEC3_0 (REGISTERS_BASE + 0x8060) /* VLYNQ_HW_INT3TO0_CFG*/ 383 #define VL1_INT_VEC7_4 (REGISTERS_BASE + 0x8064) /* VLYNQ_HW_INT7TO4_CFG*/ 384 /* VLYNQ Remote configuration registers*/ 385 #define VL1_REM_REV_ID (REGISTERS_BASE + 0x8080) /* VLYNQ_REM_REVISION*/ 386 #define VL1_REM_CTL (REGISTERS_BASE + 0x8084) /* VLYNQ_REM_ CONTROL*/ 387 #define VL1_REM_STS (REGISTERS_BASE + 0x8088) /* VLYNQ_REM_STATUS*/ 388 #define VLYNQ_REM_INTVEC (REGISTERS_BASE + 0x808C) 389 #define VL1_REM_INT_STS (REGISTERS_BASE + 0x8090) /* VLYNQ_REM_INTCR*/ 390 #define VL1_REM_INT_PEND (REGISTERS_BASE + 0x8094) /* VLYNQ_REM_INTSR*/ 391 #define VL1_REM_INT_PTR (REGISTERS_BASE + 0x8098) /* VLYNQ_REM_INTPTR*/ 392 #define VL1_REM_TX_ADDR (REGISTERS_BASE + 0x809C) /* VLYNQ_REM_TX_MAP_ADDR*/ 393 #define VL1_REM_RX_SIZE1 (REGISTERS_BASE + 0x80A0) /* VLYNQ_REM_RX_MAP_SIZE1*/ 394 #define VL1_REM_RX_OFF1 (REGISTERS_BASE + 0x80A4) /* VLYNQ_REM_RX_MAP_OFFSET1*/ 395 #define VL1_REM_RX_SIZE2 (REGISTERS_BASE + 0x80A8) /* VLYNQ_REM_RX_MAP_SIZE2*/ 396 #define VL1_REM_RX_OFF2 (REGISTERS_BASE + 0x80AC) /* VLYNQ_REM_RX_MAP_OFFSET2*/ 397 #define VL1_REM_RX_SIZE3 (REGISTERS_BASE + 0x80B0) /* VLYNQ_REM_RX_MAP_SIZE3*/ 398 #define VL1_REM_RX_OFF3 (REGISTERS_BASE + 0x80B4) /* VLYNQ_REM_RX_MAP_OFFSET3*/ 399 #define VL1_REM_RX_SIZE4 (REGISTERS_BASE + 0x80B8) /* VLYNQ_REM_RX_MAP_SIZE4*/ 400 #define VL1_REM_RX_OFF4 (REGISTERS_BASE + 0x80BC) /* VLYNQ_REM_RX_MAP_OFFSET4*/ 401 #define VL1_REM_CHIP_VER (REGISTERS_BASE + 0x80C0) /* VLYNQ_REM_CHIP_VER*/ 402 #define VLYNQ_REM_AUTONEG (REGISTERS_BASE + 0x80C4) 403 #define VLYNQ_REM_MANNEG (REGISTERS_BASE + 0x80C8) 404 #define VLYNQ_REM_NEGSTAT (REGISTERS_BASE + 0x80CC) 405 #define VLYNQ_REM_ENDIAN (REGISTERS_BASE + 0x80DC) 406 #define VL1_REM_INT_VEC3_0 (REGISTERS_BASE + 0x80E0) /* VLYNQ_REM_HW_INT3TO0_CFG*/ 407 #define VL1_REM_INT_VEC7_4 (REGISTERS_BASE + 0x80E4) /* VLYNQ_REM_HW_INT7TO4_CFG*/ 408 409 /* PCIIF*/ 410 /**/ 411 #define PCI_ID_REG (REGISTERS_BASE + 0x8400) 412 #define PCI_STATUS_SET_REG (REGISTERS_BASE + 0x8410) 413 #define PCI_STATUS_CLR_REG (REGISTERS_BASE + 0x8414) 414 #define PCI_HIMASK_SET_REG (REGISTERS_BASE + 0x8420) 415 #define PCI_HIMASK_CLR_REG (REGISTERS_BASE + 0x8424) 416 #define PCI_AMASK_SET_REG (REGISTERS_BASE + 0x8430) 417 #define PCI_AMASK_CLR_REG (REGISTERS_BASE + 0x8434) 418 #define PCI_CLKRUN_REG (REGISTERS_BASE + 0x8438) 419 #define PCI_BE_VENDOR_ID_REG (REGISTERS_BASE + 0x8500) 420 #define PCI_BE_COMMAND_REG (REGISTERS_BASE + 0x8504) 421 #define PCI_BE_REVISION_REG (REGISTERS_BASE + 0x8508) 422 #define PCI_BE_CL_SIZE_REG (REGISTERS_BASE + 0x850C) 423 #define PCI_BE_BAR0_MASK_REG (REGISTERS_BASE + 0x8510) 424 #define PCI_BE_BAR1_MASK_REG (REGISTERS_BASE + 0x8514) 425 #define PCI_BE_BAR2_MASK_REG (REGISTERS_BASE + 0x8518) 426 #define PCI_BE_BAR3_MASK_REG (REGISTERS_BASE + 0x851C) 427 #define PCI_BE_CIS_PTR_REG (REGISTERS_BASE + 0x8528) 428 #define PCI_BE_SUBSYS_ID_REG (REGISTERS_BASE + 0x852C) 429 #define PCI_BE_CAP_PTR_REG (REGISTERS_BASE + 0x8534) 430 #define PCI_BE_INTR_LINE_REG (REGISTERS_BASE + 0x853C) 431 #define PCI_BE_PM_CAP_REG (REGISTERS_BASE + 0x8540) 432 #define PCI_BE_PM_CTRL_REG (REGISTERS_BASE + 0x8544) 433 #define PCI_BE_PM_D0_CTRL_REG (REGISTERS_BASE + 0x8560) 434 #define PCI_BE_PM_D1_CTRL_REG (REGISTERS_BASE + 0x8564) 435 #define PCI_BE_PM_D2_CTRL_REG (REGISTERS_BASE + 0x8568) 436 #define PCI_BE_PM_D3_CTRL_REG (REGISTERS_BASE + 0x856C) 437 #define PCI_BE_SLV_CFG_REG (REGISTERS_BASE + 0x8580) 438 #define PCI_BE_ARB_CTRL_REG (REGISTERS_BASE + 0x8584) 439 440 #define FER (REGISTERS_BASE + 0x85A0) /* PCI_BE_STSCHG_FE_REG*/ 441 #define FEMR (REGISTERS_BASE + 0x85A4) /* PCI_BE_STSCHG_FEM_REG*/ 442 #define FPSR (REGISTERS_BASE + 0x85A8) /* PCI_BE_STSCHG_FPS_REG*/ 443 #define FFER (REGISTERS_BASE + 0x85AC) /* PCI_BE_STSCHG_FFE_REG*/ 444 445 #define PCI_BE_BAR0_TRANS_REG (REGISTERS_BASE + 0x85C0) 446 #define PCI_BE_BAR1_TRANS_REG (REGISTERS_BASE + 0x85C4) 447 #define PCI_BE_BAR2_TRANS_REG (REGISTERS_BASE + 0x85C8) 448 #define PCI_BE_BAR3_TRANS_REG (REGISTERS_BASE + 0x85CC) 449 #define PCI_BE_BAR4_TRANS_REG (REGISTERS_BASE + 0x85D0) 450 #define PCI_BE_BAR5_TRANS_REG (REGISTERS_BASE + 0x85D4) 451 #define PCI_BE_BAR0_REG (REGISTERS_BASE + 0x85E0) 452 #define PCI_BE_BAR1_REG (REGISTERS_BASE + 0x85E4) 453 #define PCI_BE_BAR2_REG (REGISTERS_BASE + 0x85E8) 454 #define PCI_BE_BAR3_REG (REGISTERS_BASE + 0x85EC) 455 456 #define PCI_PROXY_DATA (REGISTERS_BASE + 0x8700) 457 #define PCI_PROXY_ADDR (REGISTERS_BASE + 0x8704) 458 #define PCI_PROXY_CMD (REGISTERS_BASE + 0x8708) 459 #define PCI_CONTROL (REGISTERS_BASE + 0x8710) 460 461 /* USB1.1 registers*/ 462 /**/ 463 #define USB_STS_CLR (REGISTERS_BASE + 0x4000) 464 #define USB_STS_ND (REGISTERS_BASE + 0x4004) 465 #define USB_INT_ACK (REGISTERS_BASE + 0x4008) 466 #define USB_MASK (REGISTERS_BASE + 0x400c) 467 #define USB_MASK_SET (REGISTERS_BASE + 0x4010) 468 #define USB_MASK_CLR (REGISTERS_BASE + 0x4014) 469 #define USB_WU (REGISTERS_BASE + 0x4018) 470 #define USB_EP0_OUT_PTR (REGISTERS_BASE + 0x401c) 471 #define USB_EP0_OUT_VLD (REGISTERS_BASE + 0x4020) 472 #define USB_EP0_OUT_LEN (REGISTERS_BASE + 0x4024) 473 #define USB_EP0_IN_PTR (REGISTERS_BASE + 0x4028) 474 #define USB_EP0_IN_VLD (REGISTERS_BASE + 0x402c) 475 #define USB_EP0_IN_LEN (REGISTERS_BASE + 0x4030) 476 #define USB_EP1_CFG (REGISTERS_BASE + 0x4034) 477 #define USB_EP1_OUT_INT_CFG (REGISTERS_BASE + 0x4038) 478 #define USB_EP1_OUT_PTR (REGISTERS_BASE + 0x403c) 479 #define USB_EP1_OUT_VLD (REGISTERS_BASE + 0x4040) 480 #define USB_EP1_OUT_CUR_MBLK (REGISTERS_BASE + 0x4044) 481 #define USB_EP1_OUT_LEN (REGISTERS_BASE + 0x4048) 482 #define USB_EP1_IN_START_MBLK (REGISTERS_BASE + 0x404c) 483 #define USB_EP1_IN_LAST_MBLK (REGISTERS_BASE + 0x4050) 484 #define USB_EP1_IN_VLD (REGISTERS_BASE + 0x4054) 485 486 #define USB_EP2_PTR (REGISTERS_BASE + 0x405c) 487 #define USB_EP2_VLD (REGISTERS_BASE + 0x4060) 488 #define USB_EP2_LEN (REGISTERS_BASE + 0x4064) 489 #define USB_EP3_OUT_PTR0 (REGISTERS_BASE + 0x4068) 490 #define USB_EP3_OUT_VLD0 (REGISTERS_BASE + 0x406c) 491 #define USB_EP3_OUT_LEN0 (REGISTERS_BASE + 0x4070) 492 #define USB_EP3_OUT_PTR1 (REGISTERS_BASE + 0x4074) 493 #define USB_EP3_OUT_VLD1 (REGISTERS_BASE + 0x4078) 494 #define USB_EP3_OUT_LEN1 (REGISTERS_BASE + 0x407c) 495 #define USB_EP3_IN_PTR0 (REGISTERS_BASE + 0x4080) 496 #define USB_EP3_IN_VLD0 (REGISTERS_BASE + 0x4084) 497 #define USB_EP3_IN_LEN0 (REGISTERS_BASE + 0x4088) 498 #define USB_EP3_IN_PTR1 (REGISTERS_BASE + 0x408c) 499 #define USB_EP3_IN_VLD1 (REGISTERS_BASE + 0x4090) 500 #define USB_EP3_IN_LEN1 (REGISTERS_BASE + 0x4094) 501 #define USB_EP1_OUT_END_MBLK (REGISTERS_BASE + 0x4098) 502 #define USB_EP0_OUT_SETUP (REGISTERS_BASE + 0x409c) 503 #define USB_EP0_STALL (REGISTERS_BASE + 0x40a0) 504 #define USB_EP1_IN_OFFSET (REGISTERS_BASE + 0x40a4) 505 506 /* Device Configuration registers*/ 507 #define SOR_CFG (REGISTERS_BASE + 0x0800) 508 #define ECPU_CTRL (REGISTERS_BASE + 0x0804) 509 #define HI_CFG (REGISTERS_BASE + 0x0808) 510 #define EE_START (REGISTERS_BASE + 0x080C) 511 512 /* IO Control registers*/ 513 #define SERIAL_HOST_IOCFG0 (REGISTERS_BASE + 0x0894) /* new*/ 514 #define SERIAL_HOST_IOCFG1 (REGISTERS_BASE + 0x0898) /* new*/ 515 #define SERIAL_HOST_IOCFG2 (REGISTERS_BASE + 0x089C) /* new*/ 516 #define SERIAL_HOST_IOCFG3 (REGISTERS_BASE + 0x08A0) /* new*/ 517 #define GPIO_IOCFG0 (REGISTERS_BASE + 0x08F4) /* new*/ 518 #define GPIO_IOCFG1 (REGISTERS_BASE + 0x08F8) /* new*/ 519 #define GPIO_IOCFG2 (REGISTERS_BASE + 0x08FC) /* new*/ 520 #define GPIO_IOCFG3 (REGISTERS_BASE + 0x0900) /* new*/ 521 #define CHIP_ID_B (REGISTERS_BASE + 0x5674) /* new*/ 522 #define CHIP_ID CHIP_ID_B/* Leave for TNETW compatability*/ 523 #define CHIP_ID_1273_PG10 (0x04030101) 524 #define CHIP_ID_1273_PG20 (0x04030111) 525 526 #define SYSTEM (REGISTERS_BASE + 0x0810) 527 #define PCI_ARB_CFG (REGISTERS_BASE + 0x0814) 528 #define BOOT_IRAM_CFG (REGISTERS_BASE + 0x0818) 529 #define IO_CONTROL_ENABLE (REGISTERS_BASE + 0x5450) 530 #define MBLK_CFG (REGISTERS_BASE + 0x5460) 531 #define RS232_BITINTERVAL (REGISTERS_BASE + 0x0824) 532 #define TEST_PORT (REGISTERS_BASE + 0x096C) 533 #define DEBUG_PORT (REGISTERS_BASE + 0x0970) 534 #define HOST_WR_ACCESS_REG (REGISTERS_BASE + 0x09F8) 535 536 /* GPIO registers*/ 537 #define GPIO_OE (REGISTERS_BASE + 0x082C) /* 22 GPIOs*/ 538 #define GPIO_OUT (REGISTERS_BASE + 0x0834) 539 #define GPIO_IN (REGISTERS_BASE + 0x0830) 540 #define GPO_CFG (REGISTERS_BASE + 0x083C) 541 #define GPIO_SELECT (REGISTERS_BASE + 0x614C) 542 #define GPIO_OE_RADIO (REGISTERS_BASE + 0x6140) 543 #define PWRDN_BUS_L (REGISTERS_BASE + 0x0844) 544 #define PWRDN_BUS_H (REGISTERS_BASE + 0x0848) 545 #define DIE_ID_L (REGISTERS_BASE + 0x088C) 546 #define DIE_ID_H (REGISTERS_BASE + 0x0890) 547 548 /* Power Management registers*/ 549 /* */ 550 #define ELP_START (REGISTERS_BASE + 0x5800) 551 #define ELP_CFG_MODE (REGISTERS_BASE + 0x5804) 552 #define ELP_CMD (REGISTERS_BASE + 0x5808) 553 #define PLL_CAL_TIME (REGISTERS_BASE + 0x5810) 554 #define CLK_REQ_TIME (REGISTERS_BASE + 0x5814) 555 #define CLK_BUF_TIME (REGISTERS_BASE + 0x5818) 556 557 #define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820) /* Points to the CFG_PLL_SYNC_CNT_xx registers set*/ 558 #define CFG_PLL_SYNC_CNT_I (REGISTERS_BASE + 0x5820) 559 #define CFG_PLL_SYNC_CNT_II (REGISTERS_BASE + 0x5824) 560 #define CFG_PLL_SYNC_CNT_III (REGISTERS_BASE + 0x5828) 561 562 #define CFG_ELP_SLEEP_CNT (REGISTERS_BASE + 0x5830) /* Points to the CFG_ELP_SLEEP_CNT_xx registers set*/ 563 #define CFG_ELP_SLEEP_CNT_I (REGISTERS_BASE + 0x5830) 564 #define CFG_ELP_SLEEP_CNT_II (REGISTERS_BASE + 0x5834) 565 #define CFG_ELP_SLEEP_CNT_III (REGISTERS_BASE + 0x5838) 566 #define CFG_ELP_SLEEP_CNT_IV (REGISTERS_BASE + 0x583c) 567 568 #define ELP_SLEEP_CNT (REGISTERS_BASE + 0x5840) /* Points to the ELP_SLEEP_CNT_xx registers set*/ 569 #define ELP_SLEEP_CNT_I (REGISTERS_BASE + 0x5840) 570 #define ELP_SLEEP_CNT_II (REGISTERS_BASE + 0x5844) 571 #define ELP_SLEEP_CNT_III (REGISTERS_BASE + 0x5848) 572 #define ELP_SLEEP_CNT_IV (REGISTERS_BASE + 0x584c) 573 574 #define ELP_WAKE_UP_STS (REGISTERS_BASE + 0x5850) 575 #define CFG_SLP_CLK_SEL (REGISTERS_BASE + 0x5860) 576 #define CFG_SLP_CLK_EN (REGISTERS_BASE + 0x5870) 577 578 #define CFG_WAKE_UP_EN_I (REGISTERS_BASE + 0x5880) 579 #define CFG_WAKE_UP_EN_II (REGISTERS_BASE + 0x5884) 580 #define CFG_WAKE_UP_EN_III (REGISTERS_BASE + 0x5888) 581 582 #define CFG_ELP_PWRDN_I (REGISTERS_BASE + 0x5890) 583 #define CFG_ELP_PWRDN_II (REGISTERS_BASE + 0x5894) 584 #define CFG_ELP_PWRDN_III (REGISTERS_BASE + 0x5898) 585 586 #define CFG_POWER_DOWN_I (REGISTERS_BASE + 0x58a0) 587 #define CFG_POWER_DOWN_II (REGISTERS_BASE + 0x58a4) 588 #define CFG_POWER_DOWN_III (REGISTERS_BASE + 0x58a8) 589 590 #define CFG_BUCK_TESTMODE_I (REGISTERS_BASE + 0x58b0) 591 #define CFG_BUCK_TESTMODE_II (REGISTERS_BASE + 0x58b4) 592 593 #define POWER_STATUS_I (REGISTERS_BASE + 0x58C0) 594 #define POWER_STATUS_II (REGISTERS_BASE + 0x58C4) 595 596 #define DIGLDO_BIAS_PROG_I (REGISTERS_BASE + 0x58d0) 597 #define DIGLDO_BIAS_PROG_II (REGISTERS_BASE + 0x58d4) 598 599 #define LDO2P8_BIAS_PROG_I (REGISTERS_BASE + 0x58e0) 600 #define LDO2P8_BIAS_PROG_II (REGISTERS_BASE + 0x58e4) 601 602 #define ADCLDO_BIAS_PROG (REGISTERS_BASE + 0x58f0) 603 604 #define REFSYS_PROG_I (REGISTERS_BASE + 0x5910) 605 #define REFSYS_PROG_II (REGISTERS_BASE + 0x5914) 606 607 #define PM_TEST_I (REGISTERS_BASE + 0x5920) 608 #define PM_TEST_II (REGISTERS_BASE + 0x5924) 609 610 #define POR_PROG (REGISTERS_BASE + 0x5930) 611 612 #define TEST_PIN_DIR_I (REGISTERS_BASE + 0x5940) 613 #define TEST_PIN_DIR_II (REGISTERS_BASE + 0x5944) 614 615 #define PROC_CTL (REGISTERS_BASE + 0x5950) 616 617 #define ADC_REF_WAKEUP_I (REGISTERS_BASE + 0x5960) 618 #define ADC_REF_WAKEUP_II (REGISTERS_BASE + 0x5964) 619 #define ADC_REF_WAKEUP_III (REGISTERS_BASE + 0x5968) 620 #define ADC_REF_WAKEUP_IV (REGISTERS_BASE + 0x596C) 621 622 #define VREG_WAKEUP_I (REGISTERS_BASE + 0x5970) 623 #define VREG_WAKEUP_II (REGISTERS_BASE + 0x5974) 624 #define VREG_WAKEUP_III (REGISTERS_BASE + 0x5978) 625 #define VREG_WAKEUP_IV (REGISTERS_BASE + 0x597C) 626 627 #define PLL_WAKEUP_I (REGISTERS_BASE + 0x5980) 628 #define PLL_WAKEUP_II (REGISTERS_BASE + 0x5984) 629 #define PLL_WAKEUP_III (REGISTERS_BASE + 0x5988) 630 #define PLL_WAKEUP_IV (REGISTERS_BASE + 0x598C) 631 632 #define XTALOSC_WAKEUP_I (REGISTERS_BASE + 0x5990) 633 #define XTALOSC_WAKEUP_II (REGISTERS_BASE + 0x5994) 634 #define XTALOSC_WAKEUP_III (REGISTERS_BASE + 0x5998) 635 #define XTALOSC_WAKEUP_IV (REGISTERS_BASE + 0x599C) 636 637 /* ----------*/ 638 639 #define PLL_PARAMETERS (REGISTERS_BASE + 0x6040) 640 #define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008) 641 #define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100) 642 643 /* ----------*/ 644 645 #define POWER_MGMT2 (REGISTERS_BASE + 0x0840) 646 #define POWER_MGMT (REGISTERS_BASE + 0x5098) 647 #define MAC_HW_DOZE (REGISTERS_BASE + 0x090c) 648 #define ECPU_SLEEP (REGISTERS_BASE + 0x0840) 649 #define DOZE_CFG (REGISTERS_BASE + 0x54bc) 650 #define DOZE2_CFG (REGISTERS_BASE + 0x081c) 651 #define WAKEUP_CFG (REGISTERS_BASE + 0x54c0) 652 #define WAKEUP_TIME_L (REGISTERS_BASE + 0x54c8) 653 #define WAKEUP_TIME_H (REGISTERS_BASE + 0x54c4) 654 655 /**/ 656 657 /*#define CPU_WAIT_CFG (f0020)*/ 658 /*#define CFG_QOS_ACM (f0046)*/ 659 660 /* Scratch Pad registers*/ 661 #define SCR_PAD0 (REGISTERS_BASE + 0x5608) 662 #define SCR_PAD1 (REGISTERS_BASE + 0x560C) 663 #define SCR_PAD2 (REGISTERS_BASE + 0x5610) 664 #define SCR_PAD3 (REGISTERS_BASE + 0x5614) 665 #define SCR_PAD4 (REGISTERS_BASE + 0x5618) 666 #define SCR_PAD4_SET (REGISTERS_BASE + 0x561C) 667 #define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620) 668 #define SCR_PAD5 (REGISTERS_BASE + 0x5624) 669 #define SCR_PAD5_SET (REGISTERS_BASE + 0x5628) 670 #define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C) 671 #define SCR_PAD6 (REGISTERS_BASE + 0x5630) 672 #define SCR_PAD7 (REGISTERS_BASE + 0x5634) 673 #define SCR_PAD8 (REGISTERS_BASE + 0x5638) 674 #define SCR_PAD9 (REGISTERS_BASE + 0x563C) 675 676 /* Spare registers*/ 677 #define SPARE_A1 (REGISTERS_BASE + 0x0994) 678 #define SPARE_A2 (REGISTERS_BASE + 0x0998) 679 #define SPARE_A3 (REGISTERS_BASE + 0x099C) 680 #define SPARE_A4 (REGISTERS_BASE + 0x09A0) 681 #define SPARE_A5 (REGISTERS_BASE + 0x09A4) 682 #define SPARE_A6 (REGISTERS_BASE + 0x09A8) 683 #define SPARE_A7 (REGISTERS_BASE + 0x09AC) 684 #define SPARE_A8 (REGISTERS_BASE + 0x09B0) 685 #define SPARE_B1 (REGISTERS_BASE + 0x5420) 686 #define SPARE_B2 (REGISTERS_BASE + 0x5424) 687 #define SPARE_B3 (REGISTERS_BASE + 0x5428) 688 #define SPARE_B4 (REGISTERS_BASE + 0x542C) 689 #define SPARE_B5 (REGISTERS_BASE + 0x5430) 690 #define SPARE_B6 (REGISTERS_BASE + 0x5434) 691 #define SPARE_B7 (REGISTERS_BASE + 0x5438) 692 #define SPARE_B8 (REGISTERS_BASE + 0x543C) 693 694 /* RMAC registers (Raleigh MAC)*/ 695 696 /* Station registers*/ 697 #define DEV_MODE (REGISTERS_BASE + 0x5464) 698 #define STA_ADDR_L (REGISTERS_BASE + 0x546C) 699 #define STA_ADDR_H (REGISTERS_BASE + 0x5470) 700 #define BSSID_L (REGISTERS_BASE + 0x5474) 701 #define BSSID_H (REGISTERS_BASE + 0x5478) 702 #define AID_CFG (REGISTERS_BASE + 0x547C) 703 #define BASIC_RATE_CFG (REGISTERS_BASE + 0x4C6C) 704 #define BASIC_RATE_TX_CFG (REGISTERS_BASE + 0x55F0) 705 706 /* Protocol timers registers*/ 707 #define IFS_CFG0 (REGISTERS_BASE + 0x5494) 708 #define IFS_CFG1 (REGISTERS_BASE + 0x5498) 709 #define TIMEOUT_CFG (REGISTERS_BASE + 0x549C) 710 #define CONT_WIND_CFG (REGISTERS_BASE + 0x54A0) 711 #define BCN_INT_CFG (REGISTERS_BASE + 0x54A4) 712 #define RETRY_CFG (REGISTERS_BASE + 0x54A8) 713 #define DELAY_CFG (REGISTERS_BASE + 0x54B0) 714 715 /* Hardware Override registers*/ 716 #define CCA_CFG (REGISTERS_BASE + 0x54CC) 717 #define CCA_FILTER_CFG (REGISTERS_BASE + 0x5480) 718 #define RADIO_PLL_CFG (REGISTERS_BASE + 0x555C) 719 #define CCA_MON (REGISTERS_BASE + 0x54D0) 720 #define TX_FRM_CTL (REGISTERS_BASE + 0x54D4) 721 #define CONT_TX_EN (REGISTERS_BASE + 0x50EC) 722 #define PHY_STANDBY_EN (REGISTERS_BASE + 0x5668) 723 724 /* Transmit Setup registers*/ 725 #define TX_PING_PONG (REGISTERS_BASE + 0x5090) 726 #define TX_CFG0 (REGISTERS_BASE + 0x5000) 727 #define TX_CFG1 (REGISTERS_BASE + 0x5004) 728 #define TX_CFG2 (REGISTERS_BASE + 0x5008) 729 #define MAX_LIFETIME (REGISTERS_BASE + 0x50FC) 730 #define TX_PANG_SEL (REGISTERS_BASE + 0x50E0) 731 #define TX_PANG0 (REGISTERS_BASE + 0x50A0) 732 #define TX_PING0 (REGISTERS_BASE + 0x5010) 733 #define TX_PONG0 (REGISTERS_BASE + 0x5050) 734 #define TX_PANG1 (REGISTERS_BASE + 0x50A4) 735 #define TX_PING1 (REGISTERS_BASE + 0x5014) 736 #define TX_PONG1 (REGISTERS_BASE + 0x5054) 737 #define TX_PANG2 (REGISTERS_BASE + 0x50A8) 738 #define TX_PING2 (REGISTERS_BASE + 0x5018) 739 #define TX_PONG2 (REGISTERS_BASE + 0x5058) 740 #define TX_PANG3 (REGISTERS_BASE + 0x50AC) 741 #define TX_PING3 (REGISTERS_BASE + 0x501C) 742 #define TX_PONG3 (REGISTERS_BASE + 0x505C) 743 #define TX_PANG4 (REGISTERS_BASE + 0x50B0) 744 #define TX_PING4 (REGISTERS_BASE + 0x5020) 745 #define TX_PONG4 (REGISTERS_BASE + 0x5060) 746 #define TX_PANG5 (REGISTERS_BASE + 0x50B4) 747 #define TX_PING5 (REGISTERS_BASE + 0x5024) 748 #define TX_PONG5 (REGISTERS_BASE + 0x5064) 749 #define TX_PANG6 (REGISTERS_BASE + 0x50B8) 750 #define TX_PING6 (REGISTERS_BASE + 0x5028) 751 #define TX_PONG6 (REGISTERS_BASE + 0x5068) 752 #define TX_PANG7 (REGISTERS_BASE + 0x50BC) 753 #define TX_PING7 (REGISTERS_BASE + 0x502C) 754 #define TX_PONG7 (REGISTERS_BASE + 0x506C) 755 #define TX_PANG8 (REGISTERS_BASE + 0x50C0) 756 #define TX_PING8 (REGISTERS_BASE + 0x5030) 757 #define TX_PONG8 (REGISTERS_BASE + 0x5070) 758 #define TX_PANG9 (REGISTERS_BASE + 0x50C4) 759 #define TX_PING9 (REGISTERS_BASE + 0x5034) 760 #define TX_PONG9 (REGISTERS_BASE + 0x5074) 761 #define TX_PANG10 (REGISTERS_BASE + 0x50C8) 762 #define TX_PING10 (REGISTERS_BASE + 0x5038) 763 #define TX_PONG10 (REGISTERS_BASE + 0x5078) 764 #define TX_PANG11 (REGISTERS_BASE + 0x50CC) 765 #define TX_PING11 (REGISTERS_BASE + 0x503C) 766 #define TX_PONG11 (REGISTERS_BASE + 0x507C) 767 768 /* Transmit Status registers*/ 769 #define TX_STATUS (REGISTERS_BASE + 0x509C) 770 #define TX_PANG_EXCH (REGISTERS_BASE + 0x50D0) 771 #define TX_PING_EXCH (REGISTERS_BASE + 0x5040) 772 #define TX_PONG_EXCH (REGISTERS_BASE + 0x5080) 773 #define TX_PANG_ATT (REGISTERS_BASE + 0x50D4) 774 #define TX_PING_ATT (REGISTERS_BASE + 0x5044) 775 #define TX_PONG_ATT (REGISTERS_BASE + 0x5084) 776 #define TX_PANG_TIMESTAMP (REGISTERS_BASE + 0x50DC) 777 #define TX_PING_TIMESTAMP (REGISTERS_BASE + 0x504C) 778 #define TX_PONG_TIMESTAMP (REGISTERS_BASE + 0x508C) 779 780 /* Transmit State registers*/ 781 #define TX_STATE (REGISTERS_BASE + 0x5094) 782 #define TX_PANG_OVRD_CFG (REGISTERS_BASE + 0x50D8) 783 #define TX_PING_OVRD_CFG (REGISTERS_BASE + 0x5048) 784 #define TX_PONG_OVRD_CFG (REGISTERS_BASE + 0x5088) 785 #define TX_HOLD_CFG (REGISTERS_BASE + 0x54D8) 786 #define TSF_ADJ_CFG1 (REGISTERS_BASE + 0x54DC) 787 #define TSF_ADJ_CFG2 (REGISTERS_BASE + 0x54E0) 788 #define TSF_ADJ_CFG3 (REGISTERS_BASE + 0x54E4) 789 #define TSF_ADJ_CFG4 (REGISTERS_BASE + 0x54E8) 790 #define CFG_OFDM_TIMES0 (REGISTERS_BASE + 0x5648) 791 #define CFG_OFDM_TIMES1 (REGISTERS_BASE + 0x564C) 792 793 /* Beacon/Probe Response registers*/ 794 #define PRB_ADDR (REGISTERS_BASE + 0x54EC) 795 #define PRB_LENGTH (REGISTERS_BASE + 0x54F0) 796 #define BCN_ADDR (REGISTERS_BASE + 0x54F4) 797 #define BCN_LENGTH (REGISTERS_BASE + 0x54F8) 798 #define TIM_VALID0 (REGISTERS_BASE + 0x54FC) 799 #define TIM_ADDR0 (REGISTERS_BASE + 0x5500) 800 #define TIM_LENGTH0 (REGISTERS_BASE + 0x5504) 801 #define TIM_VALID1 (REGISTERS_BASE + 0x5654) 802 #define TIM_ADDR1 (REGISTERS_BASE + 0x5658) 803 #define TIM_LENGTH1 (REGISTERS_BASE + 0x565C) 804 #define TIM_SELECT (REGISTERS_BASE + 0x5660) 805 #define TSF_CFG (REGISTERS_BASE + 0x5508) 806 807 /* Other Hardware Generated Frames regi*/ 808 #define CTL_FRM_CFG (REGISTERS_BASE + 0x550C) 809 #define MGMT_FRM_CFG (REGISTERS_BASE + 0x5510) 810 #define CFG_ANT_SEL (REGISTERS_BASE + 0x5664) 811 #define RMAC_ADDR_BASE (REGISTERS_BASE + 0x5680) /* new*/ 812 813 /* Protocol Interface Read Write Interf*/ 814 #define TXSIFS_TIMER (REGISTERS_BASE + 0x4C00) 815 #define TXPIFS_TIMER (REGISTERS_BASE + 0x4C04) 816 #define TXDIFS_TIMER (REGISTERS_BASE + 0x4C08) 817 #define SLOT_TIMER (REGISTERS_BASE + 0x4C0C) 818 #define BACKOFF_TIMER (REGISTERS_BASE + 0x4C10) 819 #define BCN_PSP_TIMER (REGISTERS_BASE + 0x4C14) 820 #define NAV (REGISTERS_BASE + 0x4C18) 821 #define TSF_L (REGISTERS_BASE + 0x4C1C) 822 #define TSF_H (REGISTERS_BASE + 0x4C20) 823 #define TSF_PREV_L (REGISTERS_BASE + 0x4CC4) /* new */ 824 #define TSF_PREV_H (REGISTERS_BASE + 0x4CC8) /* new */ 825 #define TOUT_TIMER (REGISTERS_BASE + 0x4C2C) 826 #define NEXT_TBTT_L (REGISTERS_BASE + 0x4C30) 827 #define NEXT_TBTT_H (REGISTERS_BASE + 0x4C34) 828 #define DTIM_CNT (REGISTERS_BASE + 0x4C38) 829 #define CONT_WIND (REGISTERS_BASE + 0x4C3C) 830 #define PRSP_REQ (REGISTERS_BASE + 0x4C40) 831 #define PRSP_DA_L (REGISTERS_BASE + 0x4C44) 832 #define PRSP_DA_H (REGISTERS_BASE + 0x4C48) 833 #define PRSP_RETRY (REGISTERS_BASE + 0x4C4C) 834 #define PSPOLL_REQ (REGISTERS_BASE + 0x4C50) 835 #define NEXT_SEQ_NUM (REGISTERS_BASE + 0x4C54) 836 #define PRSP_SEQ_NUM (REGISTERS_BASE + 0x4C58) 837 #define BCN_SEQ_NUM (REGISTERS_BASE + 0x4C5C) 838 #define MED_USAGE (REGISTERS_BASE + 0x4C24) 839 #define MED_USAGE_TM (REGISTERS_BASE + 0x4C28) 840 #define PRB_DLY (REGISTERS_BASE + 0x4C60) 841 #define STA_SRC (REGISTERS_BASE + 0x4C64) 842 #define STA_LRC (REGISTERS_BASE + 0x4C68) 843 #define CFG_ACM (REGISTERS_BASE + 0x4C70) 844 #define RAND_NUMB (REGISTERS_BASE + 0x4C6C) 845 #define CFG_ACK_CTS_DOT11A (REGISTERS_BASE + 0x4C74) 846 #define CFG_ACK_CTS_DOT11B (REGISTERS_BASE + 0x4C78) 847 #define ACM_IFS_CFG0 (REGISTERS_BASE + 0x4C7C) 848 #define ACM_IFS_CFG1 (REGISTERS_BASE + 0x4C80) 849 #define ACM_IFS_CFG2 (REGISTERS_BASE + 0x4C84) 850 #define ACM_IFS_CFG3 (REGISTERS_BASE + 0x4C88) 851 #define ACK_CTS_FRM_CFG (REGISTERS_BASE + 0x4C8C) 852 #define CFG_RX_TSTMP_DLY0 (REGISTERS_BASE + 0x4C90) 853 #define CFG_RX_TSTMP_DLY1 (REGISTERS_BASE + 0x4C94) 854 #define CFG_RX_TSTMP_DLY2 (REGISTERS_BASE + 0x4C98) 855 #define CFG_RX_TSTMP_DLY3 (REGISTERS_BASE + 0x4C9C) 856 #define CCA_BUSY (REGISTERS_BASE + 0x4CA0) 857 #define CCA_BUSY_CLR (REGISTERS_BASE + 0x4CA4) 858 #define CCA_IDLE (REGISTERS_BASE + 0x4CA8) 859 #define CCA_IDLE_CLR (REGISTERS_BASE + 0x4CAC) 860 861 /* Receive Manager registers*/ 862 #define RX_HEAD_PTR (REGISTERS_BASE + 0x567C) /* new*/ 863 #define RX_TAIL_PTR (REGISTERS_BASE + 0x4898) /* new*/ 864 #define RX_CURR_PTR (REGISTERS_BASE + 0x5678) /* new*/ 865 #define RX_RESET (REGISTERS_BASE + 0x4800) 866 #define RX_MODMODE (REGISTERS_BASE + 0x4838) /* new*/ 867 #define MAC_HEADER_BYTECNT (REGISTERS_BASE + 0x4890) 868 #define RX_MAC_BYTECNT_INT (REGISTERS_BASE + 0x489C) 869 #define MAC_HEADER_WORD0 (REGISTERS_BASE + 0x4868) 870 #define MAC_HEADER_WORD1 (REGISTERS_BASE + 0x486C) 871 #define MAC_HEADER_WORD2 (REGISTERS_BASE + 0x4870) 872 #define MAC_HEADER_WORD3 (REGISTERS_BASE + 0x4874) 873 #define MAC_HEADER_WORD4 (REGISTERS_BASE + 0x4878) 874 #define MAC_HEADER_WORD5 (REGISTERS_BASE + 0x487C) 875 #define MAC_HEADER_WORD6 (REGISTERS_BASE + 0x4880) 876 #define MAC_HEADER_WORD7 (REGISTERS_BASE + 0x4884) 877 #define MAC_HEADER_WORD8 (REGISTERS_BASE + 0x4888) 878 #define MAC_HEADER_WORD9 (REGISTERS_BASE + 0x488C) 879 #define RX_CFG (REGISTERS_BASE + 0x5514) 880 #define RX_FILTER_CFG (REGISTERS_BASE + 0x55B4) 881 #define RX_MC0_L (REGISTERS_BASE + 0x5518) 882 #define RX_MC0_H (REGISTERS_BASE + 0x551C) 883 #define RX_MC1_L (REGISTERS_BASE + 0x5520) 884 #define RX_MC1_H (REGISTERS_BASE + 0x5524) 885 #define STA_SSID0 (REGISTERS_BASE + 0x4804) 886 #define STA_SSID1 (REGISTERS_BASE + 0x4808) 887 #define STA_SSID2 (REGISTERS_BASE + 0x480C) 888 #define STA_SSID3 (REGISTERS_BASE + 0x4810) 889 #define STA_SSID4 (REGISTERS_BASE + 0x4814) 890 #define STA_SSID5 (REGISTERS_BASE + 0x4818) 891 #define STA_SSID6 (REGISTERS_BASE + 0x481C) 892 #define STA_SSID7 (REGISTERS_BASE + 0x4820) 893 #define SSID_LEN (REGISTERS_BASE + 0x4824) 894 #define RX_FREE_MEM (REGISTERS_BASE + 0x5528) 895 #define RX_CURR_MEM (REGISTERS_BASE + 0x552C) 896 #define MAC_TIMESTAMP (REGISTERS_BASE + 0x5560) /* Check place*/ 897 #define RX_TIMESTAMP (REGISTERS_BASE + 0x5564) 898 #define RX_FRM_PTR (REGISTERS_BASE + 0x5568) 899 #define RX_FRM_LEN (REGISTERS_BASE + 0x556C) 900 #define RX_PLCP_HDR (REGISTERS_BASE + 0x5570) 901 #define RX_PLCP_SIGNAL (REGISTERS_BASE + 0x5574) 902 #define RX_PLCP_SERVICE (REGISTERS_BASE + 0x5578) /* 16 bits ?*/ 903 #define RX_PLCP_LENGTH (REGISTERS_BASE + 0x557C) 904 #define RX_FRM_CTL (REGISTERS_BASE + 0x5580) 905 #define RX_DUR_ID (REGISTERS_BASE + 0x5584) 906 #define RX_ADDR1_L (REGISTERS_BASE + 0x5588) 907 #define RX_ADDR1_H (REGISTERS_BASE + 0x558C) 908 #define RX_ADDR2_L (REGISTERS_BASE + 0x5590) 909 #define RX_ADDR2_H (REGISTERS_BASE + 0x5594) 910 #define RX_ADDR3_L (REGISTERS_BASE + 0x5598) 911 #define RX_ADDR3_H (REGISTERS_BASE + 0x559C) 912 #define RX_SEQ_CTL (REGISTERS_BASE + 0x55A0) 913 #define RX_WEP_IV (REGISTERS_BASE + 0x55A4) 914 #define RX_TIME_L (REGISTERS_BASE + 0x55A8) 915 #define RX_TIME_H (REGISTERS_BASE + 0x55AC) 916 #define RX_STATUS (REGISTERS_BASE + 0x55B0) 917 #define PLCP_ERR_CNT (REGISTERS_BASE + 0x4828) 918 #define FCS_ERR_CNT (REGISTERS_BASE + 0x482C) 919 #define RX_OVERFLOW_CNT (REGISTERS_BASE + 0x4830) 920 #define RX_DEBUG1 (REGISTERS_BASE + 0x4858) 921 #define RX_DEBUG2 (REGISTERS_BASE + 0x485C) 922 #define RX_QOS_CFG (REGISTERS_BASE + 0x4848) 923 #define RX_QOS_CTL (REGISTERS_BASE + 0x4844) 924 #define RX_QOS_STATUS (REGISTERS_BASE + 0x4854) /* new name RX_QOS_STS*/ 925 #define RX_TXOP_HOLDER_L (REGISTERS_BASE + 0x484C) 926 #define RX_TXOP_HOLDER_H (REGISTERS_BASE + 0x4850) 927 #define RX_FRM_CNT (REGISTERS_BASE + 0x4834) /* what is RX_FRM_CTR*/ 928 #define CONS_FCS_ERR_CNT (REGISTERS_BASE + 0x483C) 929 #define CONS_FCS_ERR_CFG (REGISTERS_BASE + 0x4840) 930 #define RX_QOS_CTL_MASK (REGISTERS_BASE + 0x48A0) /* new*/ 931 #define RX_QOS_ACK_EN (REGISTERS_BASE + 0x48A4) /* new*/ 932 #define RX_QOS_NOACK_EN (REGISTERS_BASE + 0x48A8) /* new*/ 933 #define RX_QOS_ACK_BITMAP (REGISTERS_BASE + 0x48AC) /* new*/ 934 935 /* Baseband Processor registers*/ 936 #define SBB_CFG (REGISTERS_BASE + 0x55C8) 937 #define SBB_ADDR (REGISTERS_BASE + 0x55D0) 938 #define SBB_DATA (REGISTERS_BASE + 0x55D4) 939 #define SBB_CTL (REGISTERS_BASE + 0x55D8) 940 941 /* Radio Control Interface registers*/ 942 #define RCI_CTL (REGISTERS_BASE + 0x55DC) 943 #define RCI_DATA (REGISTERS_BASE + 0x55E0) 944 #define RCI_CFG1 (REGISTERS_BASE + 0x55E4) 945 #define RCI_CFG2 (REGISTERS_BASE + 0x55E8) 946 #define RCI_CFG3 (REGISTERS_BASE + 0x55EC) 947 948 #define TNET1150_LAST_REG_ADDR PCI_CONTROL 949 950 #define ECPU_CONTROL_HALT 0x00000101 951 952 /*0x03bc00 address is 1KB from end of FW RAM in 125x chip*/ 953 #define FW_STATIC_NVS_TRAGET_ADDRESS 0x03bc00 954 955 /* Command mail box address */ 956 #define CMD_MBOX_ADDRESS 0x407B4 957 958 /* Top Register */ 959 #define INDIRECT_REG1 (REGISTERS_BASE + 0x9B0) 960 #define OCP_POR_CTR (REGISTERS_BASE + 0x9B4) 961 #define OCP_POR_WDATA (REGISTERS_BASE + 0x9B8) 962 #define OCP_DATA_RD (REGISTERS_BASE + 0x9BC) 963 #define OCP_CMD (REGISTERS_BASE + 0x9C0) 964 #define FUNC7_SEL 0xC8C 965 #define FUNC7_PULL 0xCB0 966 #define FN0_CCCR_REG_32 0x64 967 968 #define PLL_PARAMETERS_CLK_VAL_19_2M 0x01 969 #define PLL_PARAMETERS_CLK_VAL_26M 0x02 970 #define PLL_PARAMETERS_CLK_VAL_38_4M 0x03 971 #define PLL_PARAMETERS_CLK_VAL_52M 0x04 972 973 #define WU_COUNTER_PAUSE_VAL 0x3FF 974 975 /* Base band clocker register */ 976 #define WELP_ARM_COMMAND_VAL 0x4 977 978 /* Command mail box address */ 979 #define CMD_MBOX_ADDRESS 0x407B4 980 981 #endif 982