1 /* 2 * BusDrv.h 3 * 4 * Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /** \file BusDrv.h 36 * \brief Bus-Driver module API definition 37 * 38 * \see SdioBusDrv.c, WspiBusDrv.c 39 */ 40 41 #ifndef __BUS_DRV_API_H__ 42 #define __BUS_DRV_API_H__ 43 44 45 #include "TxnDefs.h" 46 #include "queue.h" 47 48 49 /************************************************************************ 50 * Defines 51 ************************************************************************/ 52 53 #define WSPI_PAD_LEN_WRITE 4 54 #define WSPI_PAD_LEN_READ 8 55 #define MAX_XFER_BUFS 4 56 57 #define TXN_PARAM_STATUS_OK 0 58 #define TXN_PARAM_STATUS_ERROR 1 59 #define TXN_PARAM_STATUS_RECOVERY 2 60 61 #define TXN_DIRECTION_WRITE 0 62 #define TXN_DIRECTION_READ 1 63 64 #define TXN_HIGH_PRIORITY 0 65 #define TXN_LOW_PRIORITY 1 66 #define TXN_NUM_PRIORITYS 2 67 68 #define TXN_INC_ADDR 0 69 #define TXN_FIXED_ADDR 1 70 71 #define TXN_AGGREGATE_OFF 0 72 #define TXN_AGGREGATE_ON 1 73 74 #define TXN_NON_SLEEP_ELP 1 75 #define TXN_SLEEP_ELP 0 76 77 #define NUM_OF_PARTITION 4 78 79 /************************************************************************ 80 * Macros 81 ************************************************************************/ 82 /* Get field from TTxnStruct->uTxnParams */ 83 #define TXN_PARAM_GET_PRIORITY(pTxn) ( (pTxn->uTxnParams & 0x00000003) >> 0 ) 84 #define TXN_PARAM_GET_FUNC_ID(pTxn) ( (pTxn->uTxnParams & 0x0000000C) >> 2 ) 85 #define TXN_PARAM_GET_DIRECTION(pTxn) ( (pTxn->uTxnParams & 0x00000010) >> 4 ) 86 #define TXN_PARAM_GET_FIXED_ADDR(pTxn) ( (pTxn->uTxnParams & 0x00000020) >> 5 ) 87 #define TXN_PARAM_GET_MORE(pTxn) ( (pTxn->uTxnParams & 0x00000040) >> 6 ) 88 #define TXN_PARAM_GET_SINGLE_STEP(pTxn) ( (pTxn->uTxnParams & 0x00000080) >> 7 ) 89 #define TXN_PARAM_GET_STATUS(pTxn) ( (pTxn->uTxnParams & 0x00000F00) >> 8 ) 90 #define TXN_PARAM_GET_AGGREGATE(pTxn) ( (pTxn->uTxnParams & 0x00001000) >> 12 ) 91 #define TXN_PARAM_GET_END_OF_BURST(pTxn) ( (pTxn->uTxnParams & 0x00002000) >> 13 ) 92 93 94 95 /* Set field in TTxnStruct->uTxnParams */ 96 #define TXN_PARAM_SET_PRIORITY(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000003) | (uValue << 0 ) ) 97 #define TXN_PARAM_SET_FUNC_ID(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x0000000C) | (uValue << 2 ) ) 98 #define TXN_PARAM_SET_DIRECTION(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000010) | (uValue << 4 ) ) 99 #define TXN_PARAM_SET_FIXED_ADDR(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000020) | (uValue << 5 ) ) 100 #define TXN_PARAM_SET_MORE(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000040) | (uValue << 6 ) ) 101 #define TXN_PARAM_SET_SINGLE_STEP(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000080) | (uValue << 7 ) ) 102 #define TXN_PARAM_SET_STATUS(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000F00) | (uValue << 8 ) ) 103 #define TXN_PARAM_SET_AGGREGATE(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00001000) | (uValue << 12 ) ) 104 #define TXN_PARAM_SET_END_OF_BURST(pTxn, uValue)( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00002000) | (uValue << 13 ) ) 105 106 107 #define TXN_PARAM_SET(pTxn, uPriority, uId, uDirection, uAddrMode) \ 108 TXN_PARAM_SET_PRIORITY(pTxn, uPriority); \ 109 TXN_PARAM_SET_FUNC_ID(pTxn, uId); \ 110 TXN_PARAM_SET_DIRECTION(pTxn, uDirection); \ 111 TXN_PARAM_SET_FIXED_ADDR(pTxn, uAddrMode); 112 113 #define BUILD_TTxnStruct(pTxn, uAddr, pBuf, uLen, fCB, hCB) \ 114 pTxn->aBuf[0] = (TI_UINT8*)(pBuf); \ 115 pTxn->aLen[0] = (TI_UINT16)(uLen); \ 116 pTxn->aLen[1] = 0; \ 117 pTxn->uHwAddr = uAddr; \ 118 pTxn->hCbHandle = (void*)hCB; \ 119 pTxn->fTxnDoneCb = (TTxnDoneCb)fCB; 120 121 122 /************************************************************************ 123 * Types 124 ************************************************************************/ 125 /* The TxnDone CB called by the bus driver upon Async Txn completion */ 126 typedef void (*TBusDrvTxnDoneCb)(TI_HANDLE hCbHandle, void *pTxn); 127 128 /* The TxnDone CB called by the TxnQueue upon Async Txn completion */ 129 typedef void (*TTxnQueueDoneCb)(TI_HANDLE hCbHandle, void *pTxn); 130 131 /* The TxnDone CB of the specific Txn originator (Xfer layer) called upon Async Txn completion */ 132 typedef void (*TTxnDoneCb)(TI_HANDLE hCbHandle, void *pTxn); 133 134 /* The transactions structure */ 135 typedef struct 136 { 137 TQueNodeHdr tTxnQNode; /* Header for queueing */ 138 TI_UINT32 uTxnParams; /* Txn attributes (bit fields) - see macros above */ 139 TI_UINT32 uHwAddr; /* Physical (32 bits) HW Address */ 140 TTxnDoneCb fTxnDoneCb; /* CB called by TwIf upon Async Txn completion (may be NULL) */ 141 TI_HANDLE hCbHandle; /* The handle to use when calling fTxnDoneCb */ 142 TI_UINT16 aLen[MAX_XFER_BUFS]; /* Lengths of the following aBuf data buffers respectively. 143 Zero length marks last used buffer, or MAX_XFER_BUFS of all are used. */ 144 TI_UINT8* aBuf[MAX_XFER_BUFS]; /* Host data buffers to be written to or read from the device */ 145 TI_UINT8 aWspiPad[WSPI_PAD_LEN_READ]; /* Padding used by WSPI bus driver for its header or fixed-busy bytes */ 146 } TTxnStruct; 147 148 /* Parameters for all bus types configuration in ConnectBus process */ 149 150 typedef struct 151 { 152 TI_UINT32 uBlkSizeShift; 153 TI_UINT32 uBusDrvThreadPriority; 154 } TSdioCfg; 155 156 typedef struct 157 { 158 TI_UINT32 uDummy; 159 } TWspiCfg; 160 161 typedef struct 162 { 163 TI_UINT32 uBaudRate; 164 } TUartCfg; 165 166 typedef union 167 { 168 TSdioCfg tSdioCfg; 169 TWspiCfg tWspiCfg; 170 TUartCfg tUartCfg; 171 172 } TBusDrvCfg; 173 174 175 typedef struct 176 { 177 TI_UINT32 uMemAdrr; 178 TI_UINT32 uMemSize; 179 } TPartition; 180 181 182 /************************************************************************ 183 * Functions 184 ************************************************************************/ 185 TI_HANDLE busDrv_Create (TI_HANDLE hOs); 186 TI_STATUS busDrv_Destroy (TI_HANDLE hBusDrv); 187 void busDrv_Init (TI_HANDLE hBusDrv, TI_HANDLE hReport); 188 TI_STATUS busDrv_ConnectBus (TI_HANDLE hBusDrv, 189 TBusDrvCfg *pBusDrvCfg, 190 TBusDrvTxnDoneCb fCbFunc, 191 TI_HANDLE hCbArg, 192 TBusDrvTxnDoneCb fConnectCbFunc, 193 TI_UINT32 *pRxDmaBufLen, 194 TI_UINT32 *pTxDmaBufLen); 195 TI_STATUS busDrv_DisconnectBus (TI_HANDLE hBusDrv); 196 ETxnStatus busDrv_Transact (TI_HANDLE hBusDrv, TTxnStruct *pTxn); 197 198 199 #endif /*__BUS_DRV_API_H__*/ 200 201