261 #define eepro_full_reset(ioaddr)	outb(RESET_CMD, ioaddr); udelay(40);
265 					outb(SEL_RESET_CMD, ioaddr); \
271 #define	eepro_clear_int(ioaddr)	outb(ALL_MASK, ioaddr + STATUS_REG)
274 #define	eepro_en_rx(ioaddr)	outb(RCV_ENABLE_CMD, ioaddr)
277 #define	eepro_dis_rx(ioaddr)	outb(RCV_DISABLE_CMD, ioaddr)
280 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
281 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
282 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
307 		outb(temp_reg & 0xEF, ioaddr + eeprom_reg);  in eepro_reset()
309 		outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i);  in eepro_reset()
312 	outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop  in eepro_reset()
315 	outb(temp_reg | 0x14, ioaddr + REG2);  in eepro_reset()
317 	outb(temp_reg & 0x3F, ioaddr + REG3);	/* clear test mode */  in eepro_reset()
321 	outb(RCV_LOWER_LIMIT, ioaddr + RCV_LOWER_LIMIT_REG);  in eepro_reset()
322 	outb(RCV_UPPER_LIMIT, ioaddr + RCV_UPPER_LIMIT_REG);  in eepro_reset()
323 	outb(XMT_LOWER_LIMIT, ioaddr + xmt_lower_limit_reg);  in eepro_reset()
324 	outb(XMT_UPPER_LIMIT, ioaddr + xmt_upper_limit_reg);  in eepro_reset()
353 	outb(0x40, ioaddr + STATUS_REG);  in eepro_poll()
427 	outb(XMT_CMD, ioaddr);  in eepro_transmit()
454 	outb(STOP_RCV_CMD, ioaddr);  in eepro_disable()
471 		outb(0x00, ioaddr + STATUS_REG);  in read_eeprom()
474 	outb(ctrl_val, ee_addr);  in read_eeprom()
478 		outb(outval, ee_addr);  in read_eeprom()
479 		outb(outval | EESK, ee_addr);	/* EEPROM clock tick */  in read_eeprom()
481 		outb(outval, ee_addr);		/* finish EEPROM clock tick */  in read_eeprom()
484 	outb(ctrl_val, ee_addr);  in read_eeprom()
486 		outb(ctrl_val | EESK, ee_addr);  in read_eeprom()
489 		outb(ctrl_val, ee_addr);  in read_eeprom()
494 	outb(ctrl_val | EESK, ee_addr);  in read_eeprom()
496 	outb(ctrl_val, ee_addr);  in read_eeprom()