262 #define CSR0            0x00  macro
518            SK_NAME, SK_read_reg(CSR0)));  in SK_poll()
521     csr0 = SK_read_reg(CSR0);      /* store register for checking */  in SK_poll()
528     SK_write_reg(CSR0, csr0 & CSR0_CLRALL);  in SK_poll()
611     SK_write_reg(CSR0, CSR0_INEA); /* Enable Interrupts */  in SK_poll()
632            SK_NAME, SK_read_reg(CSR0)));  in SK_transmit()
664 	SK_write_reg(CSR0, CSR0_TDMD | CSR0_INEA);  in SK_transmit()
666     csr0 = SK_read_reg(CSR0);      /* store register for checking */  in SK_transmit()
673     SK_write_reg(CSR0, csr0 & CSR0_CLRALL);  in SK_transmit()
720     SK_write_reg(CSR0, CSR0_INEA); /* Enable Interrupts */  in SK_transmit()
734            SK_NAME, SK_read_reg(CSR0)));  in SK_disable()
736            (int) SK_read_reg(CSR0)));  in SK_disable()
738     SK_write_reg(CSR0, CSR0_STOP); /* STOP the LANCE */  in SK_disable()
862                SK_NAME, SK_read_reg(CSR0));  in SK_probe1()
863         SK_write_reg(CSR0, CSR0_STOP);  in SK_probe1()
865                SK_NAME, SK_read_reg(CSR0));  in SK_probe1()
868                SK_NAME, SK_read_reg(CSR0));  in SK_probe1()
869         SK_write_reg(CSR0, CSR0_STOP);  in SK_probe1()
871                SK_NAME, SK_read_reg(CSR0));  in SK_probe1()
874                SK_NAME, SK_read_reg(CSR0));  in SK_probe1()
884                SK_NAME, SK_read_reg(CSR0)));  in SK_probe1()
905            SK_NAME, SK_read_reg(CSR0)));  in SK_lance_init()
992            SK_NAME, SK_read_reg(CSR0)));  in SK_lance_init()
1001     SK_write_reg(CSR0, CSR0_INIT);  in SK_lance_init()
1005     SK_set_RAP(CSR0);              /* Register Address Pointer to CSR0 */  in SK_lance_init()
1014 		SK_NAME, (int) SK_read_reg(CSR0),  in SK_lance_init()
1028     SK_write_reg(CSR0, CSR0_IDON | CSR0_INEA | CSR0_STRT);  in SK_lance_init()
1031             SK_read_reg(CSR0)));  in SK_lance_init()