Lines Matching refs:phy
612 u16 i, data0, data1, data2, data3, phy;
614 phy = priv->phy[priv->phyNum];
618 } else if ( phy <= TLAN_PHY_MAX_ADDR ) {
619 printk( "TLAN: Device %s, PHY 0x%02x.\n", dev->name, phy );
623 TLan_MiiReadReg( dev, phy, i, &data0 );
625 TLan_MiiReadReg( dev, phy, i + 1, &data1 );
627 TLan_MiiReadReg( dev, phy, i + 2, &data2 );
629 TLan_MiiReadReg( dev, phy, i + 3, &data3 );
661 u32 phy;
671 priv->phy[0] = TLAN_PHY_MAX_ADDR;
673 priv->phy[0] = TLAN_PHY_NONE;
676 priv->phy[1] = TLAN_PHY_NONE;
677 for ( phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++ ) {
678 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control );
679 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi );
680 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo );
682 TLAN_DBG( TLAN_DEBUG_GNRL, "PHY found at %02x %04x %04x %04x\n", phy, control, hi, lo );
683 if ( ( priv->phy[1] == TLAN_PHY_NONE ) && ( phy != TLAN_PHY_MAX_ADDR ) ) {
684 priv->phy[1] = phy;
689 if ( priv->phy[1] != TLAN_PHY_NONE ) {
691 } else if ( priv->phy[0] != TLAN_PHY_NONE ) {
707 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
708 …if ( ( priv->phyNum == 0 ) && ( priv->phy[1] != TLAN_PHY_NONE ) && ( ! ( priv->adapter->flags & TL…
710 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value );
729 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
742 u16 phy;
745 phy = priv->phy[priv->phyNum];
750 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, value );
751 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
753 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
770 u16 phy;
774 phy = priv->phy[priv->phyNum];
776 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
777 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &ability );
784 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0000);
788 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0100);
791 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2000);
795 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2100);
799 TLan_MiiWriteReg( dev, phy, MII_AN_ADV, (ability << 5) | 1);
801 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1000 );
803 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1200 );
823 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tctl );
836 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, control );
838 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tctl );
855 u16 phy;
858 phy = priv->phy[priv->phyNum];
860 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
862 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
879 TLan_MiiReadReg( dev, phy, MII_AN_ADV, &an_adv );
880 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &an_lpa );
898 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB | MII_GC_DUPLEX );
901 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB );
935 u16 phy;
938 phy = priv->phy[priv->phyNum];
941 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &phy_status );
1002 int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val )
1027 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */
1162 void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val )
1183 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */
1368 u32 phy[2];
2381 u32 phy = priv->phy[priv->phyNum];
2389 data->phy_id = phy;
3094 u32 phy;
3113 phy = priv->phy[priv->phyNum];
3121 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts );
3122 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
3125 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
3128 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
3616 u32 phy;
3625 phy = priv->phy[priv->phyNum];
3638 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 );
3639 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 );
3645 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
3647 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
3651 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner );
3652 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_PAR, &tlphy_par );
3684 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
3686 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl );