Lines Matching refs:IncomingReg
1656 bool MachineInstr::addRegisterKilled(unsigned IncomingReg, in addRegisterKilled() argument
1659 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); in addRegisterKilled()
1661 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); in addRegisterKilled()
1672 if (Reg == IncomingReg) { in addRegisterKilled()
1686 if (RegInfo->isSuperRegister(IncomingReg, Reg)) in addRegisterKilled()
1688 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterKilled()
1706 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
1729 bool MachineInstr::addRegisterDead(unsigned IncomingReg, in addRegisterDead() argument
1732 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); in addRegisterDead()
1734 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); in addRegisterDead()
1745 if (Reg == IncomingReg) { in addRegisterDead()
1751 if (RegInfo->isSuperRegister(IncomingReg, Reg)) in addRegisterDead()
1753 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterDead()
1773 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterDead()
1781 void MachineInstr::addRegisterDefined(unsigned IncomingReg, in addRegisterDefined() argument
1783 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { in addRegisterDefined()
1784 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); in addRegisterDefined()
1790 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && in addRegisterDefined()
1795 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterDefined()