Lines Matching refs:ISD
159 ISD::NodeType ExtType);
257 SDValue N3, ISD::CondCode CC,
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
402 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
412 case ISD::ConstantFP: in isNegatibleForFree()
416 case ISD::FADD: in isNegatibleForFree()
422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree()
432 case ISD::FSUB: in isNegatibleForFree()
439 case ISD::FMUL: in isNegatibleForFree()
440 case ISD::FDIV: in isNegatibleForFree()
451 case ISD::FP_EXTEND: in isNegatibleForFree()
452 case ISD::FP_ROUND: in isNegatibleForFree()
453 case ISD::FSIN: in isNegatibleForFree()
464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
472 case ISD::ConstantFP: { in GetNegatedExpression()
477 case ISD::FADD: in GetNegatedExpression()
485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
494 case ISD::FSUB: in GetNegatedExpression()
504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
507 case ISD::FMUL: in GetNegatedExpression()
508 case ISD::FDIV: in GetNegatedExpression()
526 case ISD::FP_EXTEND: in GetNegatedExpression()
527 case ISD::FSIN: in GetNegatedExpression()
531 case ISD::FP_ROUND: in GetNegatedExpression()
532 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
547 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
553 if (N.getOpcode() == ISD::SELECT_CC && in isSetCCEquivalent()
554 N.getOperand(2).getOpcode() == ISD::Constant && in isSetCCEquivalent()
555 N.getOperand(3).getOpcode() == ISD::Constant && in isSetCCEquivalent()
711 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); in ReplaceLoadWithPromotedLoad()
731 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteOperand()
732 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
733 : ISD::EXTLOAD) in PromoteOperand()
746 case ISD::AssertSext: in PromoteOperand()
747 return DAG.getNode(ISD::AssertSext, dl, PVT, in PromoteOperand()
750 case ISD::AssertZext: in PromoteOperand()
751 return DAG.getNode(ISD::AssertZext, dl, PVT, in PromoteOperand()
754 case ISD::Constant: { in PromoteOperand()
756 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
761 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
763 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); in PromoteOperand()
767 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, in SExtPromoteOperand()
849 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntBinOp()
880 if (Opc == ISD::SRA) in PromoteIntShiftOp()
882 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
896 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntShiftOp()
955 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteLoad()
956 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
957 : ISD::EXTLOAD) in PromoteLoad()
964 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); in PromoteLoad()
1044 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1045 RV.getNode()->getOpcode() != ISD::DELETED_NODE && in Run()
1097 case ISD::TokenFactor: return visitTokenFactor(N); in visit()
1098 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); in visit()
1099 case ISD::ADD: return visitADD(N); in visit()
1100 case ISD::SUB: return visitSUB(N); in visit()
1101 case ISD::ADDC: return visitADDC(N); in visit()
1102 case ISD::SUBC: return visitSUBC(N); in visit()
1103 case ISD::ADDE: return visitADDE(N); in visit()
1104 case ISD::SUBE: return visitSUBE(N); in visit()
1105 case ISD::MUL: return visitMUL(N); in visit()
1106 case ISD::SDIV: return visitSDIV(N); in visit()
1107 case ISD::UDIV: return visitUDIV(N); in visit()
1108 case ISD::SREM: return visitSREM(N); in visit()
1109 case ISD::UREM: return visitUREM(N); in visit()
1110 case ISD::MULHU: return visitMULHU(N); in visit()
1111 case ISD::MULHS: return visitMULHS(N); in visit()
1112 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); in visit()
1113 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); in visit()
1114 case ISD::SMULO: return visitSMULO(N); in visit()
1115 case ISD::UMULO: return visitUMULO(N); in visit()
1116 case ISD::SDIVREM: return visitSDIVREM(N); in visit()
1117 case ISD::UDIVREM: return visitUDIVREM(N); in visit()
1118 case ISD::AND: return visitAND(N); in visit()
1119 case ISD::OR: return visitOR(N); in visit()
1120 case ISD::XOR: return visitXOR(N); in visit()
1121 case ISD::SHL: return visitSHL(N); in visit()
1122 case ISD::SRA: return visitSRA(N); in visit()
1123 case ISD::SRL: return visitSRL(N); in visit()
1124 case ISD::CTLZ: return visitCTLZ(N); in visit()
1125 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); in visit()
1126 case ISD::CTTZ: return visitCTTZ(N); in visit()
1127 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); in visit()
1128 case ISD::CTPOP: return visitCTPOP(N); in visit()
1129 case ISD::SELECT: return visitSELECT(N); in visit()
1130 case ISD::SELECT_CC: return visitSELECT_CC(N); in visit()
1131 case ISD::SETCC: return visitSETCC(N); in visit()
1132 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
1133 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
1134 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
1135 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); in visit()
1136 case ISD::TRUNCATE: return visitTRUNCATE(N); in visit()
1137 case ISD::BITCAST: return visitBITCAST(N); in visit()
1138 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
1139 case ISD::FADD: return visitFADD(N); in visit()
1140 case ISD::FSUB: return visitFSUB(N); in visit()
1141 case ISD::FMUL: return visitFMUL(N); in visit()
1142 case ISD::FMA: return visitFMA(N); in visit()
1143 case ISD::FDIV: return visitFDIV(N); in visit()
1144 case ISD::FREM: return visitFREM(N); in visit()
1145 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); in visit()
1146 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); in visit()
1147 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); in visit()
1148 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); in visit()
1149 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); in visit()
1150 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
1151 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); in visit()
1152 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
1153 case ISD::FNEG: return visitFNEG(N); in visit()
1154 case ISD::FABS: return visitFABS(N); in visit()
1155 case ISD::FFLOOR: return visitFFLOOR(N); in visit()
1156 case ISD::FCEIL: return visitFCEIL(N); in visit()
1157 case ISD::FTRUNC: return visitFTRUNC(N); in visit()
1158 case ISD::BRCOND: return visitBRCOND(N); in visit()
1159 case ISD::BR_CC: return visitBR_CC(N); in visit()
1160 case ISD::LOAD: return visitLOAD(N); in visit()
1161 case ISD::STORE: return visitSTORE(N); in visit()
1162 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); in visit()
1163 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); in visit()
1164 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); in visit()
1165 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
1166 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
1167 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
1168 case ISD::MEMBARRIER: return visitMEMBARRIER(N); in visit()
1178 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
1181 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
1182 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
1196 case ISD::ADD: in combine()
1197 case ISD::SUB: in combine()
1198 case ISD::MUL: in combine()
1199 case ISD::AND: in combine()
1200 case ISD::OR: in combine()
1201 case ISD::XOR: in combine()
1204 case ISD::SHL: in combine()
1205 case ISD::SRA: in combine()
1206 case ISD::SRL: in combine()
1209 case ISD::SIGN_EXTEND: in combine()
1210 case ISD::ZERO_EXTEND: in combine()
1211 case ISD::ANY_EXTEND: in combine()
1214 case ISD::LOAD: in combine()
1285 case ISD::EntryToken: in visitTokenFactor()
1291 case ISD::TokenFactor: in visitTokenFactor()
1323 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), in visitTokenFactor()
1360 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && in combineShlAddConstant()
1363 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, in combineShlAddConstant()
1364 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, in combineShlAddConstant()
1366 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, in combineShlAddConstant()
1368 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); in combineShlAddConstant()
1387 if (ISD::isBuildVectorAllZeros(N1.getNode())) in visitADD()
1389 if (ISD::isBuildVectorAllZeros(N0.getNode())) in visitADD()
1394 if (N0.getOpcode() == ISD::UNDEF) in visitADD()
1396 if (N1.getOpcode() == ISD::UNDEF) in visitADD()
1400 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); in visitADD()
1403 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); in visitADD()
1410 GA->getOpcode() == ISD::GlobalAddress) in visitADD()
1415 if (N1C && N0.getOpcode() == ISD::SUB) in visitADD()
1417 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitADD()
1422 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); in visitADD()
1426 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && in visitADD()
1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); in visitADD()
1430 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && in visitADD()
1432 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); in visitADD()
1434 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) in visitADD()
1437 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) in visitADD()
1440 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADD()
1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), in visitADD()
1445 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADD()
1447 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), in visitADD()
1450 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && in visitADD()
1451 N1.getOperand(0).getOpcode() == ISD::SUB && in visitADD()
1457 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { in visitADD()
1464 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitADD()
1465 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), in visitADD()
1466 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); in visitADD()
1484 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); in visitADD()
1489 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { in visitADD()
1493 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { in visitADD()
1499 if (N1.getOpcode() == ISD::SHL && in visitADD()
1500 N1.getOperand(0).getOpcode() == ISD::SUB) in visitADD()
1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, in visitADD()
1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, in visitADD()
1508 if (N0.getOpcode() == ISD::SHL && in visitADD()
1509 N0.getOperand(0).getOpcode() == ISD::SUB) in visitADD()
1513 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, in visitADD()
1514 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, in visitADD()
1518 if (N1.getOpcode() == ISD::AND) { in visitADD()
1528 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); in visitADD()
1533 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADD()
1535 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1537 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADD()
1538 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); in visitADD()
1553 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), in visitADDC()
1554 DAG.getNode(ISD::CARRY_FALSE, in visitADDC()
1559 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); in visitADDC()
1563 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, in visitADDC()
1577 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), in visitADDC()
1578 DAG.getNode(ISD::CARRY_FALSE, in visitADDC()
1594 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), in visitADDE()
1598 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
1599 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); in visitADDE()
1611 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { in tryFoldToZero()
1615 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, in tryFoldToZero()
1626 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : in visitSUB()
1636 if (ISD::isBuildVectorAllZeros(N1.getNode())) in visitSUB()
1646 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); in visitSUB()
1649 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, in visitSUB()
1653 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); in visitSUB()
1655 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
1658 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
1661 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
1664 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { in visitSUB()
1667 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, in visitSUB()
1671 if (N0.getOpcode() == ISD::ADD && in visitSUB()
1672 (N0.getOperand(1).getOpcode() == ISD::SUB || in visitSUB()
1673 N0.getOperand(1).getOpcode() == ISD::ADD) && in visitSUB()
1678 if (N0.getOpcode() == ISD::ADD && in visitSUB()
1679 N0.getOperand(1).getOpcode() == ISD::ADD && in visitSUB()
1681 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, in visitSUB()
1684 if (N0.getOpcode() == ISD::SUB && in visitSUB()
1685 N0.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitSUB()
1691 if (N0.getOpcode() == ISD::UNDEF) in visitSUB()
1693 if (N1.getOpcode() == ISD::UNDEF) in visitSUB()
1700 if (N1C && GA->getOpcode() == ISD::GlobalAddress) in visitSUB()
1723 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), in visitSUBC()
1724 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), in visitSUBC()
1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), in visitSUBC()
1735 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), in visitSUBC()
1740 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), in visitSUBC()
1741 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), in visitSUBC()
1753 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
1754 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); in visitSUBE()
1773 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) in visitMUL()
1777 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); in visitMUL()
1780 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); in visitMUL()
1786 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitMUL()
1790 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, in visitMUL()
1798 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitMUL()
1800 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, in visitMUL()
1805 if (N1C && N0.getOpcode() == ISD::SHL && in visitMUL()
1807 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, in visitMUL()
1810 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, in visitMUL()
1819 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && in visitMUL()
1822 } else if (N1.getOpcode() == ISD::SHL && in visitMUL()
1829 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, in visitMUL()
1831 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, in visitMUL()
1837 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && in visitMUL()
1839 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, in visitMUL()
1840 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, in visitMUL()
1842 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, in visitMUL()
1846 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); in visitMUL()
1868 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); in visitSDIV()
1874 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitSDIV()
1880 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), in visitSDIV()
1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, in visitSDIV()
1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, in visitSDIV()
1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); in visitSDIV()
1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, in visitSDIV()
1916 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, in visitSDIV()
1928 if (N0.getOpcode() == ISD::UNDEF) in visitSDIV()
1931 if (N1.getOpcode() == ISD::UNDEF) in visitSDIV()
1952 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); in visitUDIV()
1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, in visitUDIV()
1959 if (N1.getOpcode() == ISD::SHL) { in visitUDIV()
1963 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, in visitUDIV()
1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); in visitUDIV()
1980 if (N0.getOpcode() == ISD::UNDEF) in visitUDIV()
1983 if (N1.getOpcode() == ISD::UNDEF) in visitUDIV()
1998 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); in visitSREM()
2003 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); in visitSREM()
2009 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); in visitSREM()
2013 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, in visitSREM()
2015 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); in visitSREM()
2022 if (N0.getOpcode() == ISD::UNDEF) in visitSREM()
2025 if (N1.getOpcode() == ISD::UNDEF) in visitSREM()
2040 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); in visitUREM()
2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, in visitUREM()
2046 if (N1.getOpcode() == ISD::SHL) { in visitUREM()
2050 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, in visitUREM()
2054 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); in visitUREM()
2062 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); in visitUREM()
2066 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, in visitUREM()
2068 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); in visitUREM()
2075 if (N0.getOpcode() == ISD::UNDEF) in visitUREM()
2078 if (N1.getOpcode() == ISD::UNDEF) in visitUREM()
2096 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, in visitMULHS()
2100 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) in visitMULHS()
2109 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2110 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2111 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2112 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2115 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHS()
2136 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) in visitMULHU()
2145 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
2147 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
2148 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHU()
2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
2151 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHU()
2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); in visitSMUL_LOHI()
2227 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitSMUL_LOHI()
2228 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); in visitSMUL_LOHI()
2229 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); in visitSMUL_LOHI()
2230 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); in visitSMUL_LOHI()
2232 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
2234 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitSMUL_LOHI()
2236 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); in visitSMUL_LOHI()
2245 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); in visitUMUL_LOHI()
2257 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitUMUL_LOHI()
2258 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); in visitUMUL_LOHI()
2259 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); in visitUMUL_LOHI()
2260 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); in visitUMUL_LOHI()
2262 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
2264 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitUMUL_LOHI()
2266 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); in visitUMUL_LOHI()
2278 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), in visitSMULO()
2288 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), in visitUMULO()
2295 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); in visitSDIVREM()
2302 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); in visitUDIVREM()
2327 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
2328 N0.getOpcode() == ISD::SIGN_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
2330 (N0.getOpcode() == ISD::ANY_EXTEND && in SimplifyBinOpWithSameOpcodeHands()
2332 (N0.getOpcode() == ISD::TRUNCATE && in SimplifyBinOpWithSameOpcodeHands()
2350 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || in SimplifyBinOpWithSameOpcodeHands()
2351 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && in SimplifyBinOpWithSameOpcodeHands()
2368 if ((N0.getOpcode() == ISD::BITCAST || in SimplifyBinOpWithSameOpcodeHands()
2369 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && in SimplifyBinOpWithSameOpcodeHands()
2393 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && in SimplifyBinOpWithSameOpcodeHands()
2394 N0.getOperand(1).getOpcode() == ISD::UNDEF && in SimplifyBinOpWithSameOpcodeHands()
2395 N1.getOperand(1).getOpcode() == ISD::UNDEF) { in SimplifyBinOpWithSameOpcodeHands()
2443 if (ISD::isBuildVectorAllZeros(N0.getNode())) in visitAND()
2445 if (ISD::isBuildVectorAllZeros(N1.getNode())) in visitAND()
2449 if (ISD::isBuildVectorAllOnes(N0.getNode())) in visitAND()
2451 if (ISD::isBuildVectorAllOnes(N1.getNode())) in visitAND()
2456 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) in visitAND()
2460 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); in visitAND()
2463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); in visitAND()
2472 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); in visitAND()
2476 if (N1C && N0.getOpcode() == ISD::OR) in visitAND()
2481 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
2486 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), in visitAND()
2505 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
2506 N0.getOperand(0).getOpcode() == ISD::LOAD) || in visitAND()
2507 N0.getOpcode() == ISD::LOAD) { in visitAND()
2508 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? in visitAND()
2553 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
2565 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; in visitAND()
2566 case ISD::ZEXTLOAD: in visitAND()
2567 case ISD::NON_EXTLOAD: B = true; break; in visitAND()
2574 if (Load->getExtensionType() == ISD::EXTLOAD) { in visitAND()
2575 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
2600 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); in visitAND()
2601 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); in visitAND()
2606 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { in visitAND()
2607 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), in visitAND()
2613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { in visitAND()
2614 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), in visitAND()
2620 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { in visitAND()
2621 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), in visitAND()
2629 Op1 = ISD::getSetCCSwappedOperands(Op1); in visitAND()
2634 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); in visitAND()
2635 if (Result != ISD::SETCC_INVALID && in visitAND()
2638 TLI.isOperationLegal(ISD::SETCC, in visitAND()
2658 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { in visitAND()
2667 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { in visitAND()
2668 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, in visitAND()
2679 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && in visitAND()
2689 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { in visitAND()
2690 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, in visitAND()
2705 if (N1C && (N0.getOpcode() == ISD::LOAD || in visitAND()
2706 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
2707 N0.getOperand(0).getOpcode() == ISD::LOAD))) { in visitAND()
2708 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; in visitAND()
2712 if (LN0->getExtensionType() != ISD::SEXTLOAD && in visitAND()
2720 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { in visitAND()
2724 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, in visitAND()
2738 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { in visitAND()
2751 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, in visitAND()
2760 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, in visitAND()
2773 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitAND()
2789 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, in visitAND()
2813 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) in MatchBSwapHWordLow()
2819 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
2821 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
2823 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
2833 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
2843 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
2845 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
2860 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
2871 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
2892 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); in MatchBSwapHWordLow()
2894 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, in MatchBSwapHWordLow()
2907 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
2926 if (Opc == ISD::AND) { in isBSwapHWordElement()
2930 if (N0.getOpcode() != ISD::SRL) in isBSwapHWordElement()
2938 if (N0.getOpcode() != ISD::SHL) in isBSwapHWordElement()
2944 } else if (Opc == ISD::SHL) { in isBSwapHWordElement()
2979 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) in MatchBSwapHWord()
2986 if (N0.getOpcode() != ISD::OR) in MatchBSwapHWord()
2991 if (N1.getOpcode() == ISD::OR && in MatchBSwapHWord()
3013 if (N00.getOpcode() != ISD::OR) in MatchBSwapHWord()
3027 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, in MatchBSwapHWord()
3033 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) in MatchBSwapHWord()
3034 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); in MatchBSwapHWord()
3035 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) in MatchBSwapHWord()
3036 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); in MatchBSwapHWord()
3037 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, in MatchBSwapHWord()
3038 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), in MatchBSwapHWord()
3039 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); in MatchBSwapHWord()
3056 if (ISD::isBuildVectorAllZeros(N0.getNode())) in visitOR()
3058 if (ISD::isBuildVectorAllZeros(N1.getNode())) in visitOR()
3062 if (ISD::isBuildVectorAllOnes(N0.getNode())) in visitOR()
3064 if (ISD::isBuildVectorAllOnes(N1.getNode())) in visitOR()
3070 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { in visitOR()
3076 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); in visitOR()
3079 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); in visitOR()
3099 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); in visitOR()
3104 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && in visitOR()
3108 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, in visitOR()
3109 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, in visitOR()
3111 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); in visitOR()
3115 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); in visitOR()
3116 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); in visitOR()
3123 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { in visitOR()
3124 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), in visitOR()
3132 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { in visitOR()
3133 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), in visitOR()
3141 Op1 = ISD::getSetCCSwappedOperands(Op1); in visitOR()
3146 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); in visitOR()
3147 if (Result != ISD::SETCC_INVALID && in visitOR()
3150 TLI.isOperationLegal(ISD::SETCC, in visitOR()
3164 if (N0.getOpcode() == ISD::AND && in visitOR()
3165 N1.getOpcode() == ISD::AND && in visitOR()
3166 N0.getOperand(1).getOpcode() == ISD::Constant && in visitOR()
3167 N1.getOperand(1).getOpcode() == ISD::Constant && in visitOR()
3179 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, in visitOR()
3181 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, in visitOR()
3200 if (Op.getOpcode() == ISD::AND) { in MatchRotateHalf()
3209 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in MatchRotateHalf()
3226 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); in MatchRotate()
3227 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); in MatchRotate()
3248 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
3261 if (LHSShiftAmt.getOpcode() == ISD::Constant && in MatchRotate()
3262 RHSShiftAmt.getOpcode() == ISD::Constant) { in MatchRotate()
3268 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
3284 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); in MatchRotate()
3297 if (RHSShiftAmt.getOpcode() == ISD::SUB && in MatchRotate()
3302 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, in MatchRotate()
3310 if (LHSShiftAmt.getOpcode() == ISD::SUB && in MatchRotate()
3315 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, in MatchRotate()
3322 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
3323 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
3324 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
3325 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
3326 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
3327 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
3328 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
3329 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
3332 if (RExtOp0.getOpcode() == ISD::SUB && in MatchRotate()
3341 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
3346 } else if (LExtOp0.getOpcode() == ISD::SUB && in MatchRotate()
3355 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, in MatchRotate()
3380 if (ISD::isBuildVectorAllZeros(N0.getNode())) in visitXOR()
3382 if (ISD::isBuildVectorAllZeros(N1.getNode())) in visitXOR()
3387 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) in visitXOR()
3390 if (N0.getOpcode() == ISD::UNDEF) in visitXOR()
3392 if (N1.getOpcode() == ISD::UNDEF) in visitXOR()
3396 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); in visitXOR()
3399 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); in visitXOR()
3404 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); in visitXOR()
3411 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), in visitXOR()
3419 case ISD::SETCC: in visitXOR()
3421 case ISD::SELECT_CC: in visitXOR()
3429 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && in visitXOR()
3433 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, in visitXOR()
3436 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); in visitXOR()
3441 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { in visitXOR()
3444 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR()
3445 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS in visitXOR()
3446 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS in visitXOR()
3453 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { in visitXOR()
3456 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR()
3457 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS in visitXOR()
3458 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS in visitXOR()
3464 if (N1C && N0.getOpcode() == ISD::XOR) { in visitXOR()
3468 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), in visitXOR()
3472 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), in visitXOR()
3508 case ISD::OR: in visitShiftByConstant()
3509 case ISD::XOR: in visitShiftByConstant()
3512 case ISD::AND: in visitShiftByConstant()
3515 case ISD::ADD: in visitShiftByConstant()
3516 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
3532 if ((BinOpLHSVal->getOpcode() != ISD::SHL && in visitShiftByConstant()
3533 BinOpLHSVal->getOpcode() != ISD::SRA && in visitShiftByConstant()
3534 BinOpLHSVal->getOpcode() != ISD::SRL) || in visitShiftByConstant()
3544 if (N->getOpcode() == ISD::SRA) { in visitShiftByConstant()
3574 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); in visitSHL()
3585 if (N0.getOpcode() == ISD::UNDEF) in visitSHL()
3592 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
3593 N1.getOperand(0).getOpcode() == ISD::AND && in visitSHL()
3601 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, in visitSHL()
3602 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, in visitSHL()
3603 DAG.getNode(ISD::TRUNCATE, in visitSHL()
3614 if (N1C && N0.getOpcode() == ISD::SHL && in visitSHL()
3615 N0.getOperand(1).getOpcode() == ISD::Constant) { in visitSHL()
3620 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), in visitSHL()
3629 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
3630 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
3631 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
3632 N0.getOperand(0).getOpcode() == ISD::SHL && in visitSHL()
3642 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, in visitSHL()
3653 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && in visitSHL()
3654 N0.getOperand(1).getOpcode() == ISD::Constant) { in visitSHL()
3663 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), in visitSHL()
3667 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), in visitSHL()
3670 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, in visitSHL()
3675 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { in visitSHL()
3681 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), in visitSHL()
3704 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); in visitSRA()
3719 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { in visitSRA()
3726 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) in visitSRA()
3727 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, in visitSRA()
3732 if (N1C && N0.getOpcode() == ISD::SRA) { in visitSRA()
3736 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), in visitSRA()
3746 if (N0.getOpcode() == ISD::SHL) { in visitSRA()
3762 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && in visitSRA()
3763 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && in visitSRA()
3768 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, in visitSRA()
3770 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, in visitSRA()
3772 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), in visitSRA()
3779 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
3780 N1.getOperand(0).getOpcode() == ISD::AND && in visitSRA()
3788 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, in visitSRA()
3789 DAG.getNode(ISD::AND, N->getDebugLoc(), in visitSRA()
3791 DAG.getNode(ISD::TRUNCATE, in visitSRA()
3800 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
3801 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
3802 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
3815 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, in visitSRA()
3817 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); in visitSRA()
3828 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); in visitSRA()
3849 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); in visitSRL()
3865 if (N1C && N0.getOpcode() == ISD::SRL && in visitSRL()
3866 N0.getOperand(1).getOpcode() == ISD::Constant) { in visitSRL()
3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), in visitSRL()
3876 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
3877 N0.getOperand(0).getOpcode() == ISD::SRL && in visitSRL()
3889 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, in visitSRL()
3890 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, in visitSRL()
3897 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && in visitSRL()
3900 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), in visitSRL()
3906 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
3912 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
3914 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, in visitSRL()
3918 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); in visitSRL()
3925 if (N0.getOpcode() == ISD::SRA) in visitSRL()
3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); in visitSRL()
3930 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
3954 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, in visitSRL()
3959 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, in visitSRL()
3965 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
3966 N1.getOperand(0).getOpcode() == ISD::AND && in visitSRL()
3974 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, in visitSRL()
3975 DAG.getNode(ISD::AND, N->getDebugLoc(), in visitSRL()
3977 DAG.getNode(ISD::TRUNCATE, in visitSRL()
4019 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
4021 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { in visitSRL()
4024 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
4038 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); in visitCTLZ()
4048 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); in visitCTLZ_ZERO_UNDEF()
4058 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); in visitCTTZ()
4068 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); in visitCTTZ_ZERO_UNDEF()
4078 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); in visitCTPOP()
4103 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); in visitSELECT()
4113 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, in visitSELECT()
4115 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, in visitSELECT()
4119 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); in visitSELECT()
4120 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); in visitSELECT()
4126 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); in visitSELECT()
4132 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); in visitSELECT()
4136 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); in visitSELECT()
4140 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); in visitSELECT()
4144 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); in visitSELECT()
4151 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
4156 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && in visitSELECT()
4157 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) in visitSELECT()
4158 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, in visitSELECT()
4173 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); in visitSELECT_CC()
4192 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) in visitSELECT_CC()
4193 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), in visitSELECT_CC()
4230 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
4231 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); in ExtendUsesToFormExtLoad()
4232 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
4253 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
4262 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
4277 ISD::NodeType ExtType) { in ExtendSetCCUses()
4292 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), in ExtendSetCCUses()
4303 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); in visitSIGN_EXTEND()
4307 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
4308 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, in visitSIGN_EXTEND()
4311 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
4342 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); in visitSIGN_EXTEND()
4347 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); in visitSIGN_EXTEND()
4351 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, in visitSIGN_EXTEND()
4354 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); in visitSIGN_EXTEND()
4356 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); in visitSIGN_EXTEND()
4357 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, in visitSIGN_EXTEND()
4366 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && in visitSIGN_EXTEND()
4368 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { in visitSIGN_EXTEND()
4372 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); in visitSIGN_EXTEND()
4375 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, in visitSIGN_EXTEND()
4382 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), in visitSIGN_EXTEND()
4386 ISD::SIGN_EXTEND); in visitSIGN_EXTEND()
4393 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && in visitSIGN_EXTEND()
4394 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { in visitSIGN_EXTEND()
4398 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { in visitSIGN_EXTEND()
4399 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, in visitSIGN_EXTEND()
4407 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), in visitSIGN_EXTEND()
4416 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitSIGN_EXTEND()
4417 N0.getOpcode() == ISD::XOR) && in visitSIGN_EXTEND()
4419 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
4420 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && in visitSIGN_EXTEND()
4423 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { in visitSIGN_EXTEND()
4427 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, in visitSIGN_EXTEND()
4430 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, in visitSIGN_EXTEND()
4441 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, in visitSIGN_EXTEND()
4447 ISD::SIGN_EXTEND); in visitSIGN_EXTEND()
4453 if (N0.getOpcode() == ISD::SETCC) { in visitSIGN_EXTEND()
4500 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))) in visitSIGN_EXTEND()
4501 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, in visitSIGN_EXTEND()
4510 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && in visitSIGN_EXTEND()
4512 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); in visitSIGN_EXTEND()
4524 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
4530 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || in isTruncateOf()
4531 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) in isTruncateOf()
4561 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); in visitZERO_EXTEND()
4564 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
4565 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4584 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); in visitZERO_EXTEND()
4586 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); in visitZERO_EXTEND()
4594 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
4608 if (N0.getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
4609 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { in visitZERO_EXTEND()
4626 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); in visitZERO_EXTEND()
4629 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); in visitZERO_EXTEND()
4638 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
4639 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
4640 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
4646 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); in visitZERO_EXTEND()
4648 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); in visitZERO_EXTEND()
4652 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4660 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && in visitZERO_EXTEND()
4662 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { in visitZERO_EXTEND()
4666 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); in visitZERO_EXTEND()
4669 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4676 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), in visitZERO_EXTEND()
4681 ISD::ZERO_EXTEND); in visitZERO_EXTEND()
4688 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitZERO_EXTEND()
4689 N0.getOpcode() == ISD::XOR) && in visitZERO_EXTEND()
4691 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
4692 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && in visitZERO_EXTEND()
4695 if (LN0->getExtensionType() != ISD::SEXTLOAD) { in visitZERO_EXTEND()
4699 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, in visitZERO_EXTEND()
4702 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, in visitZERO_EXTEND()
4713 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, in visitZERO_EXTEND()
4719 ISD::ZERO_EXTEND); in visitZERO_EXTEND()
4727 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && in visitZERO_EXTEND()
4728 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { in visitZERO_EXTEND()
4732 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { in visitZERO_EXTEND()
4733 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4741 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), in visitZERO_EXTEND()
4748 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
4762 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4766 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4782 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4784 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4797 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
4799 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitZERO_EXTEND()
4803 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
4817 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); in visitZERO_EXTEND()
4820 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), in visitZERO_EXTEND()
4833 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); in visitANY_EXTEND()
4837 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
4838 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
4839 N0.getOpcode() == ISD::SIGN_EXTEND) in visitANY_EXTEND()
4844 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
4858 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
4863 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); in visitANY_EXTEND()
4864 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); in visitANY_EXTEND()
4869 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
4870 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
4871 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
4876 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); in visitANY_EXTEND()
4878 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); in visitANY_EXTEND()
4882 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, in visitANY_EXTEND()
4890 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && in visitANY_EXTEND()
4892 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { in visitANY_EXTEND()
4896 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); in visitANY_EXTEND()
4899 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, in visitANY_EXTEND()
4906 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), in visitANY_EXTEND()
4910 ISD::ANY_EXTEND); in visitANY_EXTEND()
4918 if (N0.getOpcode() == ISD::LOAD && in visitANY_EXTEND()
4919 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && in visitANY_EXTEND()
4930 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), in visitANY_EXTEND()
4936 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
4986 case ISD::Constant: { in GetDemandedBits()
4996 case ISD::OR: in GetDemandedBits()
4997 case ISD::XOR: in GetDemandedBits()
5004 case ISD::SRL: in GetDemandedBits()
5017 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), in GetDemandedBits()
5032 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in ReduceLoadWidth()
5043 if (Opc == ISD::SIGN_EXTEND_INREG) { in ReduceLoadWidth()
5044 ExtType = ISD::SEXTLOAD; in ReduceLoadWidth()
5046 } else if (Opc == ISD::SRL) { in ReduceLoadWidth()
5048 ExtType = ISD::ZEXTLOAD; in ReduceLoadWidth()
5066 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in ReduceLoadWidth()
5083 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) in ReduceLoadWidth()
5097 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in ReduceLoadWidth()
5143 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), in ReduceLoadWidth()
5149 if (ExtType == ISD::NON_EXTLOAD) in ReduceLoadWidth()
5177 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, in ReduceLoadWidth()
5194 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) in visitSIGN_EXTEND_INREG()
5195 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); in visitSIGN_EXTEND_INREG()
5202 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
5204 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, in visitSIGN_EXTEND_INREG()
5211 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
5214 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) in visitSIGN_EXTEND_INREG()
5215 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); in visitSIGN_EXTEND_INREG()
5236 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
5243 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, in visitSIGN_EXTEND_INREG()
5249 if (ISD::isEXTLoad(N0.getNode()) && in visitSIGN_EXTEND_INREG()
5250 ISD::isUNINDEXEDLoad(N0.getNode()) && in visitSIGN_EXTEND_INREG()
5253 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { in visitSIGN_EXTEND_INREG()
5255 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, in visitSIGN_EXTEND_INREG()
5267 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && in visitSIGN_EXTEND_INREG()
5271 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { in visitSIGN_EXTEND_INREG()
5273 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, in visitSIGN_EXTEND_INREG()
5285 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
5289 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, in visitSIGN_EXTEND_INREG()
5306 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); in visitTRUNCATE()
5308 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
5309 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); in visitTRUNCATE()
5311 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
5312 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
5313 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
5320 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); in visitTRUNCATE()
5336 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
5355 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in visitTRUNCATE()
5358 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, in visitTRUNCATE()
5369 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
5370 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
5391 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &Opnds[0], in visitTRUNCATE()
5406 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); in visitTRUNCATE()
5417 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
5425 if (X.getOpcode() != ISD::UNDEF) { in visitTRUNCATE()
5449 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); in visitTRUNCATE()
5453 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, in visitTRUNCATE()
5468 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
5476 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
5480 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || in CombineConsecutiveLoads()
5486 if (ISD::isNON_EXTLoad(LD2) && in CombineConsecutiveLoads()
5498 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) in CombineConsecutiveLoads()
5516 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && in visitBITCAST()
5520 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && in visitBITCAST()
5521 N0.getOperand(i).getOpcode() != ISD::Constant && in visitBITCAST()
5522 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { in visitBITCAST()
5536 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); in visitBITCAST()
5552 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
5553 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, in visitBITCAST()
5558 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && in visitBITCAST()
5561 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { in visitBITCAST()
5574 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), in visitBITCAST()
5584 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || in visitBITCAST()
5585 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && in visitBITCAST()
5588 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, in visitBITCAST()
5593 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
5594 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, in visitBITCAST()
5596 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
5597 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, in visitBITCAST()
5605 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && in visitBITCAST()
5611 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), in visitBITCAST()
5618 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); in visitBITCAST()
5623 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), in visitBITCAST()
5627 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); in visitBITCAST()
5632 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, in visitBITCAST()
5636 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), in visitBITCAST()
5638 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, in visitBITCAST()
5642 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); in visitBITCAST()
5647 if (N0.getOpcode() == ISD::BUILD_PAIR) { in visitBITCAST()
5682 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) in ConstantFoldBITCASTofBUILD_VECTOR()
5683 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5684 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), in ConstantFoldBITCASTofBUILD_VECTOR()
5693 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); in ConstantFoldBITCASTofBUILD_VECTOR()
5694 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), in ConstantFoldBITCASTofBUILD_VECTOR()
5698 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5741 if (Op.getOpcode() == ISD::UNDEF) continue; in ConstantFoldBITCASTofBUILD_VECTOR()
5755 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5761 bool isS2V = ISD::isScalarToVector(BV); in ConstantFoldBITCASTofBUILD_VECTOR()
5768 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { in ConstantFoldBITCASTofBUILD_VECTOR()
5782 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5792 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5811 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); in visitFADD()
5814 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); in visitFADD()
5820 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && in visitFADD()
5822 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, in visitFADD()
5825 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && in visitFADD()
5827 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, in visitFADD()
5832 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && in visitFADD()
5834 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), in visitFADD()
5835 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5840 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { in visitFADD()
5846 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { in visitFADD()
5854 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && in visitFADD()
5856 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
5862 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5865 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5871 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5874 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5879 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && in visitFADD()
5882 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5885 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5890 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
5893 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5896 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5901 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
5907 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5910 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5916 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5919 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5925 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && in visitFADD()
5928 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5931 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5936 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && in visitFADD()
5939 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, in visitFADD()
5942 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5947 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
5952 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5957 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
5962 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5968 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
5972 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFADD()
5982 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { in visitFADD()
5985 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { in visitFADD()
5986 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, in visitFADD()
5992 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { in visitFADD()
5993 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, in visitFADD()
6017 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); in visitFSUB()
6027 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) in visitFSUB()
6028 return DAG.getNode(ISD::FNEG, dl, VT, N1); in visitFSUB()
6032 return DAG.getNode(ISD::FADD, dl, VT, N0, in visitFSUB()
6043 if (N1.getOpcode() == ISD::FADD) { in visitFSUB()
6060 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { in visitFSUB()
6063 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { in visitFSUB()
6064 return DAG.getNode(ISD::FMA, dl, VT, in visitFSUB()
6066 DAG.getNode(ISD::FNEG, dl, VT, N1)); in visitFSUB()
6071 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { in visitFSUB()
6072 return DAG.getNode(ISD::FMA, dl, VT, in visitFSUB()
6073 DAG.getNode(ISD::FNEG, dl, VT, in visitFSUB()
6079 if (N0.getOpcode() == ISD::FNEG && in visitFSUB()
6080 N0.getOperand(0).getOpcode() == ISD::FMUL && in visitFSUB()
6084 return DAG.getNode(ISD::FMA, dl, VT, in visitFSUB()
6085 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, in visitFSUB()
6086 DAG.getNode(ISD::FNEG, dl, VT, N1)); in visitFSUB()
6109 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); in visitFMUL()
6112 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); in visitFMUL()
6119 ISD::isBuildVectorAllZeros(N1.getNode())) in visitFMUL()
6126 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); in visitFMUL()
6129 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) in visitFMUL()
6130 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); in visitFMUL()
6140 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFMUL()
6148 N1CFP && N0.getOpcode() == ISD::FMUL && in visitFMUL()
6150 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), in visitFMUL()
6151 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFMUL()
6173 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); in visitFMA()
6175 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); in visitFMA()
6179 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); in visitFMA()
6183 N2.getOpcode() == ISD::FMUL && in visitFMA()
6185 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { in visitFMA()
6186 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
6187 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); in visitFMA()
6193 N0.getOpcode() == ISD::FMUL && N1CFP && in visitFMA()
6194 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { in visitFMA()
6195 return DAG.getNode(ISD::FMA, dl, VT, in visitFMA()
6197 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), in visitFMA()
6205 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); in visitFMA()
6208 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { in visitFMA()
6209 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); in visitFMA()
6211 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); in visitFMA()
6217 return DAG.getNode(ISD::FMUL, dl, VT, in visitFMA()
6219 DAG.getNode(ISD::FADD, dl, VT, in visitFMA()
6225 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { in visitFMA()
6226 return DAG.getNode(ISD::FMUL, dl, VT, in visitFMA()
6228 DAG.getNode(ISD::FADD, dl, VT, in visitFMA()
6252 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); in visitFDIV()
6267 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || in visitFDIV()
6269 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, in visitFDIV()
6281 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, in visitFDIV()
6299 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); in visitFREM()
6312 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); in visitFCOPYSIGN()
6319 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) in visitFCOPYSIGN()
6320 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFCOPYSIGN()
6322 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) in visitFCOPYSIGN()
6323 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, in visitFCOPYSIGN()
6324 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); in visitFCOPYSIGN()
6331 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
6332 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
6333 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, in visitFCOPYSIGN()
6337 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
6338 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFCOPYSIGN()
6341 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
6342 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, in visitFCOPYSIGN()
6347 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) in visitFCOPYSIGN()
6348 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, in visitFCOPYSIGN()
6364 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) in visitSINT_TO_FP()
6365 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); in visitSINT_TO_FP()
6369 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
6370 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
6373 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); in visitSINT_TO_FP()
6381 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { in visitSINT_TO_FP()
6383 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
6386 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { in visitSINT_TO_FP()
6391 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); in visitSINT_TO_FP()
6396 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
6397 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && in visitSINT_TO_FP()
6399 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { in visitSINT_TO_FP()
6404 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); in visitSINT_TO_FP()
6421 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) in visitUINT_TO_FP()
6422 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); in visitUINT_TO_FP()
6426 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
6427 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
6430 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); in visitUINT_TO_FP()
6438 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { in visitUINT_TO_FP()
6441 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
6443 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { in visitUINT_TO_FP()
6448 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); in visitUINT_TO_FP()
6462 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); in visitFP_TO_SINT()
6474 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); in visitFP_TO_UINT()
6487 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); in visitFP_ROUND()
6490 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
6494 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
6498 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), in visitFP_ROUND()
6503 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { in visitFP_ROUND()
6504 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, in visitFP_ROUND()
6507 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, in visitFP_ROUND()
6523 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); in visitFP_ROUND_INREG()
6536 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
6541 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); in visitFP_EXTEND()
6545 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
6550 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, in visitFP_EXTEND()
6552 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); in visitFP_EXTEND()
6556 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && in visitFP_EXTEND()
6558 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { in visitFP_EXTEND()
6560 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, in visitFP_EXTEND()
6568 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), in visitFP_EXTEND()
6592 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && in visitFNEG()
6599 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, in visitFNEG()
6602 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in visitFNEG()
6608 if (N0.getOpcode() == ISD::FMUL) { in visitFNEG()
6611 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, in visitFNEG()
6613 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, in visitFNEG()
6628 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); in visitFCEIL()
6640 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); in visitFTRUNC()
6652 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); in visitFFLOOR()
6669 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFABS()
6671 if (N0.getOpcode() == ISD::FABS) in visitFABS()
6675 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
6676 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); in visitFABS()
6681 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && in visitFABS()
6687 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, in visitFABS()
6690 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in visitFABS()
6711 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
6712 TLI.isOperationLegalOrCustom(ISD::BR_CC, in visitBRCOND()
6714 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, in visitBRCOND()
6719 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || in visitBRCOND()
6720 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && in visitBRCOND()
6722 N1.getOperand(0).getOpcode() == ISD::SRL))) { in visitBRCOND()
6724 if (N1.getOpcode() == ISD::TRUNCATE) { in visitBRCOND()
6750 if (Op0.getOpcode() == ISD::AND && in visitBRCOND()
6751 Op1.getOpcode() == ISD::Constant) { in visitBRCOND()
6754 if (AndOp1.getOpcode() == ISD::Constant) { in visitBRCOND()
6763 ISD::SETNE); in visitBRCOND()
6765 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), in visitBRCOND()
6792 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { in visitBRCOND()
6810 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), in visitBRCOND()
6820 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in visitBRCOND()
6824 Op0.getOpcode() == ISD::XOR) { in visitBRCOND()
6835 Equal ? ISD::SETEQ : ISD::SETNE); in visitBRCOND()
6841 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), in visitBRCOND()
6868 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
6869 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, in visitBR_CC()
6896 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
6904 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
6935 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && in CombineToPreIndexedLoadStore()
6936 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) in CombineToPreIndexedLoadStore()
6943 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && in CombineToPreIndexedLoadStore()
6944 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) in CombineToPreIndexedLoadStore()
6954 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
6961 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
7013 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
7103 if (AM == ISD::PRE_DEC) in CombineToPreIndexedLoadStore()
7109 if (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) in CombineToPreIndexedLoadStore()
7151 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && in CombineToPostIndexedLoadStore()
7152 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) in CombineToPostIndexedLoadStore()
7159 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && in CombineToPostIndexedLoadStore()
7160 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) in CombineToPostIndexedLoadStore()
7175 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) in CombineToPostIndexedLoadStore()
7180 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
7207 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ in CombineToPostIndexedLoadStore()
7323 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { in visitLOAD()
7324 if (ISD::isNON_TRUNCStore(Chain.getNode())) { in visitLOAD()
7356 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { in visitLOAD()
7372 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), in visitLOAD()
7399 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
7401 !ISD::isNormalLoad(V->getOperand(0).getNode())) in CheckForMaskedLoad()
7412 else if (Chain->getOpcode() != ISD::TokenFactor) in CheckForMaskedLoad()
7493 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, in ShrinkLoadReplaceStoreWithStore()
7508 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), in ShrinkLoadReplaceStoreWithStore()
7514 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); in ShrinkLoadReplaceStoreWithStore()
7547 if (Opc == ISD::OR) { in ReduceLoadOpStoreWidth()
7563 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || in ReduceLoadOpStoreWidth()
7564 Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
7568 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && in ReduceLoadOpStoreWidth()
7580 if (Opc == ISD::AND) in ReduceLoadOpStoreWidth()
7605 if (Opc == ISD::AND) in ReduceLoadOpStoreWidth()
7618 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), in ReduceLoadOpStoreWidth()
7654 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && in TransformFPLoadStorePair()
7668 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair()
7669 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair()
7670 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || in TransformFPLoadStorePair()
7671 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) in TransformFPLoadStorePair()
7704 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { in GetPointerBaseAndOffset()
7755 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) in MergeConsecutiveStores()
7767 if (BasePtr.first.getOpcode() == ISD::UNDEF) in MergeConsecutiveStores()
8035 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) in MergeConsecutiveStores()
8181 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
8189 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) in visitSTORE()
8196 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) in visitSTORE()
8205 if (Value.getOpcode() != ISD::TargetConstantFP) { in visitSTORE()
8216 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { in visitSTORE()
8227 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { in visitSTORE()
8236 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { in visitSTORE()
8253 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, in visitSTORE()
8260 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, in visitSTORE()
8307 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), in visitSTORE()
8364 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) in visitSTORE()
8386 } while (ST->getOpcode() != ISD::DELETED_NODE); in visitSTORE()
8402 if (InVal.getOpcode() == ISD::UNDEF) in visitINSERT_VECTOR_ELT()
8408 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in visitINSERT_VECTOR_ELT()
8420 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in visitINSERT_VECTOR_ELT()
8423 } else if (InVec.getOpcode() == ISD::UNDEF) { in visitINSERT_VECTOR_ELT()
8437 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in visitINSERT_VECTOR_ELT()
8438 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); in visitINSERT_VECTOR_ELT()
8443 return DAG.getNode(ISD::BUILD_VECTOR, dl, in visitINSERT_VECTOR_ELT()
8453 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
8473 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE in visitEXTRACT_VECTOR_ELT()
8494 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, in visitEXTRACT_VECTOR_ELT()
8518 if (InVec.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
8535 if (ISD::isNormalLoad(InVec.getNode())) { in visitEXTRACT_VECTOR_ELT()
8537 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
8539 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { in visitEXTRACT_VECTOR_ELT()
8564 if (InVec.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
8571 if (ISD::isNormalLoad(InVec.getNode())) { in visitEXTRACT_VECTOR_ELT()
8594 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) in visitEXTRACT_VECTOR_ELT()
8608 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, in visitEXTRACT_VECTOR_ELT()
8623 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) in visitEXTRACT_VECTOR_ELT()
8624 ? ISD::ZEXTLOAD : ISD::EXTLOAD; in visitEXTRACT_VECTOR_ELT()
8636 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); in visitEXTRACT_VECTOR_ELT()
8638 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); in visitEXTRACT_VECTOR_ELT()
8682 if (In.getOpcode() == ISD::UNDEF) continue; in reduceBuildVecExtToExtBuildVec()
8684 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
8685 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
8735 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
8736 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
8737 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); in reduceBuildVecExtToExtBuildVec()
8739 if (Cast.getOpcode() == ISD::UNDEF) in reduceBuildVecExtToExtBuildVec()
8758 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); in reduceBuildVecExtToExtBuildVec()
8763 return DAG.getNode(ISD::BITCAST, dl, VT, BV); in reduceBuildVecExtToExtBuildVec()
8773 unsigned Opcode = ISD::DELETED_NODE; in reduceBuildVecConvertToConvertBuildVec()
8780 if (Opc == ISD::UNDEF) in reduceBuildVecConvertToConvertBuildVec()
8784 if (Opcode == ISD::DELETED_NODE && in reduceBuildVecConvertToConvertBuildVec()
8785 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { in reduceBuildVecConvertToConvertBuildVec()
8808 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) in reduceBuildVecConvertToConvertBuildVec()
8821 if (In.getOpcode() == ISD::UNDEF) in reduceBuildVecConvertToConvertBuildVec()
8826 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, in reduceBuildVecConvertToConvertBuildVec()
8839 if (ISD::allOperandsUndef(N)) in visitBUILD_VECTOR()
8856 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) in visitBUILD_VECTOR()
8862 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; in visitBUILD_VECTOR()
8866 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in visitBUILD_VECTOR()
8892 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { in visitBUILD_VECTOR()
8933 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in visitBUILD_VECTOR()
8971 if (ISD::allOperandsUndef(N)) in visitCONCAT_VECTORS()
8981 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
9003 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, in visitEXTRACT_SUBVECTOR()
9008 if (V->getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
9036 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) in visitVECTOR_SHUFFLE()
9054 if (N0.getOpcode() == ISD::UNDEF) { in visitVECTOR_SHUFFLE()
9071 if (N1.getOpcode() == ISD::UNDEF) { in visitVECTOR_SHUFFLE()
9094 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
9101 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
9107 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { in visitVECTOR_SHUFFLE()
9130 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && in visitVECTOR_SHUFFLE()
9131 N1.getOpcode() == ISD::UNDEF) { in visitVECTOR_SHUFFLE()
9136 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) in visitVECTOR_SHUFFLE()
9169 case ISD::ATOMIC_CMP_SWAP: in visitMEMBARRIER()
9170 case ISD::ATOMIC_SWAP: in visitMEMBARRIER()
9171 case ISD::ATOMIC_LOAD_ADD: in visitMEMBARRIER()
9172 case ISD::ATOMIC_LOAD_SUB: in visitMEMBARRIER()
9173 case ISD::ATOMIC_LOAD_AND: in visitMEMBARRIER()
9174 case ISD::ATOMIC_LOAD_OR: in visitMEMBARRIER()
9175 case ISD::ATOMIC_LOAD_XOR: in visitMEMBARRIER()
9176 case ISD::ATOMIC_LOAD_NAND: in visitMEMBARRIER()
9177 case ISD::ATOMIC_LOAD_MIN: in visitMEMBARRIER()
9178 case ISD::ATOMIC_LOAD_MAX: in visitMEMBARRIER()
9179 case ISD::ATOMIC_LOAD_UMIN: in visitMEMBARRIER()
9180 case ISD::ATOMIC_LOAD_UMAX: in visitMEMBARRIER()
9187 if (fence.getOpcode() != ISD::MEMBARRIER) in visitMEMBARRIER()
9191 case ISD::ATOMIC_CMP_SWAP: in visitMEMBARRIER()
9196 case ISD::ATOMIC_SWAP: in visitMEMBARRIER()
9197 case ISD::ATOMIC_LOAD_ADD: in visitMEMBARRIER()
9198 case ISD::ATOMIC_LOAD_SUB: in visitMEMBARRIER()
9199 case ISD::ATOMIC_LOAD_AND: in visitMEMBARRIER()
9200 case ISD::ATOMIC_LOAD_OR: in visitMEMBARRIER()
9201 case ISD::ATOMIC_LOAD_XOR: in visitMEMBARRIER()
9202 case ISD::ATOMIC_LOAD_NAND: in visitMEMBARRIER()
9203 case ISD::ATOMIC_LOAD_MIN: in visitMEMBARRIER()
9204 case ISD::ATOMIC_LOAD_MAX: in visitMEMBARRIER()
9205 case ISD::ATOMIC_LOAD_UMIN: in visitMEMBARRIER()
9206 case ISD::ATOMIC_LOAD_UMAX: in visitMEMBARRIER()
9225 if (N->getOpcode() == ISD::AND) { in XformToShuffleWithZero()
9226 if (RHS.getOpcode() == ISD::BITCAST) in XformToShuffleWithZero()
9228 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { in XformToShuffleWithZero()
9253 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), in XformToShuffleWithZero()
9255 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); in XformToShuffleWithZero()
9257 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); in XformToShuffleWithZero()
9276 if (LHS.getOpcode() == ISD::BUILD_VECTOR && in SimplifyVBinOp()
9277 RHS.getOpcode() == ISD::BUILD_VECTOR) { in SimplifyVBinOp()
9283 if ((LHSOp.getOpcode() != ISD::UNDEF && in SimplifyVBinOp()
9284 LHSOp.getOpcode() != ISD::Constant && in SimplifyVBinOp()
9285 LHSOp.getOpcode() != ISD::ConstantFP) || in SimplifyVBinOp()
9286 (RHSOp.getOpcode() != ISD::UNDEF && in SimplifyVBinOp()
9287 RHSOp.getOpcode() != ISD::Constant && in SimplifyVBinOp()
9288 RHSOp.getOpcode() != ISD::ConstantFP)) in SimplifyVBinOp()
9292 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || in SimplifyVBinOp()
9293 N->getOpcode() == ISD::FDIV) { in SimplifyVBinOp()
9294 if ((RHSOp.getOpcode() == ISD::Constant && in SimplifyVBinOp()
9296 (RHSOp.getOpcode() == ISD::ConstantFP && in SimplifyVBinOp()
9309 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); in SimplifyVBinOp()
9311 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); in SimplifyVBinOp()
9317 if (FoldOp.getOpcode() != ISD::UNDEF && in SimplifyVBinOp()
9318 FoldOp.getOpcode() != ISD::Constant && in SimplifyVBinOp()
9319 FoldOp.getOpcode() != ISD::ConstantFP) in SimplifyVBinOp()
9326 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), in SimplifyVBinOp()
9340 if (N0.getOpcode() != ISD::BUILD_VECTOR) in SimplifyVUnaryOp()
9347 if (Op.getOpcode() != ISD::UNDEF && in SimplifyVUnaryOp()
9348 Op.getOpcode() != ISD::ConstantFP) in SimplifyVUnaryOp()
9352 if (FoldOp.getOpcode() != ISD::UNDEF && in SimplifyVUnaryOp()
9353 FoldOp.getOpcode() != ISD::ConstantFP) in SimplifyVUnaryOp()
9362 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), in SimplifyVUnaryOp()
9368 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); in SimplifySelect()
9379 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
9380 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), in SimplifySelect()
9385 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), in SimplifySelect()
9416 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
9429 LLD->getExtensionType() != ISD::EXTLOAD && in SimplifySelectOps()
9430 RLD->getExtensionType() != ISD::EXTLOAD) || in SimplifySelectOps()
9446 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
9455 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), in SimplifySelectOps()
9469 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), in SimplifySelectOps()
9478 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { in SimplifySelectOps()
9486 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? in SimplifySelectOps()
9513 ISD::CondCode CC, bool NotExtCompare) { in SimplifySelectCC()
9540 if ((CC == ISD::SETGE || CC == ISD::SETGT) && in SimplifySelectCC()
9541 N0 == N2 && N3.getOpcode() == ISD::FNEG && in SimplifySelectCC()
9543 return DAG.getNode(ISD::FABS, DL, VT, N0); in SimplifySelectCC()
9546 if ((CC == ISD::SETLT || CC == ISD::SETLE) && in SimplifySelectCC()
9547 N0 == N3 && N2.getOpcode() == ISD::FNEG && in SimplifySelectCC()
9549 return DAG.getNode(ISD::FABS, DL, VT, N3); in SimplifySelectCC()
9564 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != in SimplifySelectCC()
9592 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), in SimplifySelectCC()
9595 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, in SimplifySelectCC()
9607 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && in SimplifySelectCC()
9620 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), in SimplifySelectCC()
9625 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); in SimplifySelectCC()
9629 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); in SimplifySelectCC()
9632 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), in SimplifySelectCC()
9639 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); in SimplifySelectCC()
9643 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); in SimplifySelectCC()
9653 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
9665 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); in SimplifySelectCC()
9672 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); in SimplifySelectCC()
9674 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); in SimplifySelectCC()
9691 TLI.isOperationLegal(ISD::SETCC, in SimplifySelectCC()
9702 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), in SimplifySelectCC()
9706 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), in SimplifySelectCC()
9717 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, in SimplifySelectCC()
9729 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { in SimplifySelectCC()
9732 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); in SimplifySelectCC()
9737 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && in SimplifySelectCC()
9739 TLI.isOperationLegal(ISD::CTLZ, XType))) { in SimplifySelectCC()
9740 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); in SimplifySelectCC()
9741 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, in SimplifySelectCC()
9746 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { in SimplifySelectCC()
9747 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), in SimplifySelectCC()
9750 return DAG.getNode(ISD::SRL, DL, XType, in SimplifySelectCC()
9751 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), in SimplifySelectCC()
9756 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { in SimplifySelectCC()
9757 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, in SimplifySelectCC()
9760 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); in SimplifySelectCC()
9772 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || in SimplifySelectCC()
9773 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && in SimplifySelectCC()
9774 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) in SimplifySelectCC()
9776 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || in SimplifySelectCC()
9777 (N1C->isOne() && CC == ISD::SETLT)) && in SimplifySelectCC()
9778 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) in SimplifySelectCC()
9783 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, in SimplifySelectCC()
9787 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), in SimplifySelectCC()
9791 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); in SimplifySelectCC()
9800 SDValue N1, ISD::CondCode Cond, in SimplifySetCC()
9844 if (Base.getOpcode() == ISD::ADD) { in FindBaseOffset()
10029 case ISD::EntryToken: in GatherAllAliases()
10033 case ISD::LOAD: in GatherAllAliases()
10034 case ISD::STORE: { in GatherAllAliases()
10062 case ISD::TokenFactor: in GatherAllAliases()
10101 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, in FindBetterChain()