Lines Matching refs:mi
96 MachineInstr *mi = &*regItr; in trivialSpillEverywhere() local
98 DEBUG(dbgs() << " Processing " << *mi); in trivialSpillEverywhere()
103 } while (regItr != mri->reg_end() && (&*regItr == mi)); in trivialSpillEverywhere()
109 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { in trivialSpillEverywhere()
110 MachineOperand &op = mi->getOperand(i); in trivialSpillEverywhere()
113 hasUse |= mi->getOperand(i).isUse(); in trivialSpillEverywhere()
114 hasDef |= mi->getOperand(i).isDef(); in trivialSpillEverywhere()
125 MachineOperand &mop = mi->getOperand(mopIdx); in trivialSpillEverywhere()
127 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { in trivialSpillEverywhere()
134 MachineBasicBlock::iterator miItr(mi); in trivialSpillEverywhere()
136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newLI->reg, ss, trc, in trivialSpillEverywhere()
149 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr),newLI->reg, in trivialSpillEverywhere()