190     unsigned MOReg = MO.getReg();  in sink3AddrInstruction()
194       UseRegs.insert(MO.getReg());  in sink3AddrInstruction()
203     DefReg = MO.getReg();  in sink3AddrInstruction()
263       unsigned MOReg = MO.getReg();  in sink3AddrInstruction()
338     DstReg = MI.getOperand(0).getReg();  in isCopyToReg()
339     SrcReg = MI.getOperand(1).getReg();  in isCopyToReg()
341     DstReg = MI.getOperand(0).getReg();  in isCopyToReg()
342     SrcReg = MI.getOperand(2).getReg();  in isCopyToReg()
434     if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)  in isTwoAddrUse()
438       DstReg = MI.getOperand(ti).getReg();  in isTwoAddrUse()
590     unsigned RegA = MI->getOperand(0).getReg();  in commuteInstruction()
800     unsigned MOReg = MO.getReg();  in rescheduleMIBelowKill()
818   while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {  in rescheduleMIBelowKill()
819     Defs.insert(End->getOperand(0).getReg());  in rescheduleMIBelowKill()
843       unsigned MOReg = MO.getReg();  in rescheduleMIBelowKill()
986     unsigned MOReg = MO.getReg();  in rescheduleKillAboveMI()
1025       unsigned MOReg = MO.getReg();  in rescheduleKillAboveMI()
1098   unsigned regA = MI.getOperand(DstIdx).getReg();  in tryInstructionTransform()
1099   unsigned regB = MI.getOperand(SrcIdx).getReg();  in tryInstructionTransform()
1122       regC = MI.getOperand(regCIdx).getReg();  in tryInstructionTransform()
1232                   TargetRegisterInfo::isVirtualRegister(MO.getReg())) {  in tryInstructionTransform()
1235                     if (NewMIs[0]->killsRegister(MO.getReg()))  in tryInstructionTransform()
1236                       LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);  in tryInstructionTransform()
1238                       assert(NewMIs[1]->killsRegister(MO.getReg()) &&  in tryInstructionTransform()
1240                       LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);  in tryInstructionTransform()
1243                 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {  in tryInstructionTransform()
1244                   if (NewMIs[1]->registerDefIsDead(MO.getReg()))  in tryInstructionTransform()
1245                     LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);  in tryInstructionTransform()
1247                     assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&  in tryInstructionTransform()
1249                     LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);  in tryInstructionTransform()
1262                 OrigRegs.push_back(MOI->getReg());  in tryInstructionTransform()
1307     unsigned SrcReg = SrcMO.getReg();  in collectTiedOperands()
1308     unsigned DstReg = DstMO.getReg();  in collectTiedOperands()
1353     unsigned RegA = DstMO.getReg();  in processTiedPairs()
1357     RegB = MI->getOperand(SrcIdx).getReg();  in processTiedPairs()
1378              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1406     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&  in processTiedPairs()
1430         if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {  in processTiedPairs()
1466       if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {  in processTiedPairs()
1543           unsigned SrcReg = mi->getOperand(SrcIdx).getReg();  in runOnMachineFunction()
1544           unsigned DstReg = mi->getOperand(DstIdx).getReg();  in runOnMachineFunction()
1604   unsigned DstReg = MI->getOperand(0).getReg();  in eliminateRegSequence()
1614     OrigRegs.push_back(MI->getOperand(0).getReg());  in eliminateRegSequence()
1616       OrigRegs.push_back(MI->getOperand(i).getReg());  in eliminateRegSequence()
1622     unsigned SrcReg = UseMO.getReg();  in eliminateRegSequence()
1633         if (MI->getOperand(j).getReg() == SrcReg) {  in eliminateRegSequence()