Lines Matching refs:ISD
66 setTargetDAGCombine(ISD::ATOMIC_FENCE); in AArch64TargetLowering()
67 setTargetDAGCombine(ISD::ATOMIC_STORE); in AArch64TargetLowering()
70 setTargetDAGCombine(ISD::OR); in AArch64TargetLowering()
72 setTargetDAGCombine(ISD::AND); in AArch64TargetLowering()
73 setTargetDAGCombine(ISD::SRA); in AArch64TargetLowering()
76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
81 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); in AArch64TargetLowering()
82 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AArch64TargetLowering()
83 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in AArch64TargetLowering()
86 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
87 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in AArch64TargetLowering()
91 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AArch64TargetLowering()
92 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AArch64TargetLowering()
93 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in AArch64TargetLowering()
94 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in AArch64TargetLowering()
96 setOperationAction(ISD::SELECT, MVT::i32, Custom); in AArch64TargetLowering()
97 setOperationAction(ISD::SELECT, MVT::i64, Custom); in AArch64TargetLowering()
98 setOperationAction(ISD::SELECT, MVT::f32, Custom); in AArch64TargetLowering()
99 setOperationAction(ISD::SELECT, MVT::f64, Custom); in AArch64TargetLowering()
101 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
102 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
103 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
106 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in AArch64TargetLowering()
108 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
109 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
110 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
111 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AArch64TargetLowering()
114 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in AArch64TargetLowering()
115 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in AArch64TargetLowering()
117 setOperationAction(ISD::VASTART, MVT::Other, Custom); in AArch64TargetLowering()
118 setOperationAction(ISD::VACOPY, MVT::Other, Custom); in AArch64TargetLowering()
119 setOperationAction(ISD::VAEND, MVT::Other, Expand); in AArch64TargetLowering()
120 setOperationAction(ISD::VAARG, MVT::Other, Expand); in AArch64TargetLowering()
122 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in AArch64TargetLowering()
124 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AArch64TargetLowering()
125 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AArch64TargetLowering()
127 setOperationAction(ISD::UREM, MVT::i32, Expand); in AArch64TargetLowering()
128 setOperationAction(ISD::UREM, MVT::i64, Expand); in AArch64TargetLowering()
129 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
130 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
132 setOperationAction(ISD::SREM, MVT::i32, Expand); in AArch64TargetLowering()
133 setOperationAction(ISD::SREM, MVT::i64, Expand); in AArch64TargetLowering()
134 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
135 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
137 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in AArch64TargetLowering()
138 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in AArch64TargetLowering()
141 setOperationAction(ISD::FABS, MVT::f32, Legal); in AArch64TargetLowering()
142 setOperationAction(ISD::FABS, MVT::f64, Legal); in AArch64TargetLowering()
144 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AArch64TargetLowering()
145 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in AArch64TargetLowering()
147 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AArch64TargetLowering()
148 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in AArch64TargetLowering()
150 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in AArch64TargetLowering()
151 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in AArch64TargetLowering()
153 setOperationAction(ISD::FNEG, MVT::f32, Legal); in AArch64TargetLowering()
154 setOperationAction(ISD::FNEG, MVT::f64, Legal); in AArch64TargetLowering()
156 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AArch64TargetLowering()
157 setOperationAction(ISD::FRINT, MVT::f64, Legal); in AArch64TargetLowering()
159 setOperationAction(ISD::FSQRT, MVT::f32, Legal); in AArch64TargetLowering()
160 setOperationAction(ISD::FSQRT, MVT::f64, Legal); in AArch64TargetLowering()
162 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AArch64TargetLowering()
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in AArch64TargetLowering()
165 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AArch64TargetLowering()
166 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AArch64TargetLowering()
167 setOperationAction(ISD::ConstantFP, MVT::f128, Legal); in AArch64TargetLowering()
170 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in AArch64TargetLowering()
171 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in AArch64TargetLowering()
173 setOperationAction(ISD::FCOS, MVT::f32, Expand); in AArch64TargetLowering()
174 setOperationAction(ISD::FCOS, MVT::f64, Expand); in AArch64TargetLowering()
176 setOperationAction(ISD::FEXP, MVT::f32, Expand); in AArch64TargetLowering()
177 setOperationAction(ISD::FEXP, MVT::f64, Expand); in AArch64TargetLowering()
179 setOperationAction(ISD::FEXP2, MVT::f32, Expand); in AArch64TargetLowering()
180 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in AArch64TargetLowering()
182 setOperationAction(ISD::FLOG, MVT::f32, Expand); in AArch64TargetLowering()
183 setOperationAction(ISD::FLOG, MVT::f64, Expand); in AArch64TargetLowering()
185 setOperationAction(ISD::FLOG2, MVT::f32, Expand); in AArch64TargetLowering()
186 setOperationAction(ISD::FLOG2, MVT::f64, Expand); in AArch64TargetLowering()
188 setOperationAction(ISD::FLOG10, MVT::f32, Expand); in AArch64TargetLowering()
189 setOperationAction(ISD::FLOG10, MVT::f64, Expand); in AArch64TargetLowering()
191 setOperationAction(ISD::FPOW, MVT::f32, Expand); in AArch64TargetLowering()
192 setOperationAction(ISD::FPOW, MVT::f64, Expand); in AArch64TargetLowering()
194 setOperationAction(ISD::FPOWI, MVT::f32, Expand); in AArch64TargetLowering()
195 setOperationAction(ISD::FPOWI, MVT::f64, Expand); in AArch64TargetLowering()
197 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering()
198 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering()
200 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
201 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
203 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
204 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
208 setOperationAction(ISD::FABS, MVT::f128, Expand); in AArch64TargetLowering()
209 setOperationAction(ISD::FADD, MVT::f128, Custom); in AArch64TargetLowering()
210 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
211 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
212 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
213 setOperationAction(ISD::FMA, MVT::f128, Expand); in AArch64TargetLowering()
214 setOperationAction(ISD::FMUL, MVT::f128, Custom); in AArch64TargetLowering()
215 setOperationAction(ISD::FNEG, MVT::f128, Expand); in AArch64TargetLowering()
216 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); in AArch64TargetLowering()
217 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand); in AArch64TargetLowering()
218 setOperationAction(ISD::FPOW, MVT::f128, Expand); in AArch64TargetLowering()
219 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering()
220 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
221 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
222 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
223 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
224 setOperationAction(ISD::FSUB, MVT::f128, Custom); in AArch64TargetLowering()
225 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); in AArch64TargetLowering()
226 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
227 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in AArch64TargetLowering()
228 setOperationAction(ISD::SELECT, MVT::f128, Expand); in AArch64TargetLowering()
229 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
230 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
235 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
236 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
237 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in AArch64TargetLowering()
238 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in AArch64TargetLowering()
239 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom); in AArch64TargetLowering()
240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
241 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
242 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
243 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
244 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
245 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
246 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
247 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
252 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); in AArch64TargetLowering()
253 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in AArch64TargetLowering()
254 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand); in AArch64TargetLowering()
263 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); in AArch64TargetLowering()
264 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); in AArch64TargetLowering()
800 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_AArch64NoMoreRegs()
851 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, in SaveVarArgRegisters()
871 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, in SaveVarArgRegisters()
885 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0], in SaveVarArgRegisters()
894 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
913 ISD::ArgFlagsTy Flags = Ins[i].Flags; in LowerFormalArguments()
953 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
1008 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
1057 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
1060 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
1084 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; in LowerCall()
1086 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; in LowerCall()
1159 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
1193 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1225 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); in LowerCall()
1249 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in LowerCall()
1345 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerCallResult()
1370 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1377 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
1393 const SmallVectorImpl<ISD::OutputArg> &Outs, in IsEligibleForTailCallOptimization()
1395 const SmallVectorImpl<ISD::InputArg> &Ins, in IsEligibleForTailCallOptimization()
1535 return DAG.getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other, in addTokenForArgument()
1539 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) { in IntCCToA64CC()
1541 case ISD::SETEQ: return A64CC::EQ; in IntCCToA64CC()
1542 case ISD::SETGT: return A64CC::GT; in IntCCToA64CC()
1543 case ISD::SETGE: return A64CC::GE; in IntCCToA64CC()
1544 case ISD::SETLT: return A64CC::LT; in IntCCToA64CC()
1545 case ISD::SETLE: return A64CC::LE; in IntCCToA64CC()
1546 case ISD::SETNE: return A64CC::NE; in IntCCToA64CC()
1547 case ISD::SETUGT: return A64CC::HI; in IntCCToA64CC()
1548 case ISD::SETUGE: return A64CC::HS; in IntCCToA64CC()
1549 case ISD::SETULT: return A64CC::LO; in IntCCToA64CC()
1550 case ISD::SETULE: return A64CC::LS; in IntCCToA64CC()
1567 ISD::CondCode CC, SDValue &A64cc, in getSelectableIntSetCC()
1590 case ISD::SETLT: in getSelectableIntSetCC()
1591 case ISD::SETGE: in getSelectableIntSetCC()
1593 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getSelectableIntSetCC()
1597 case ISD::SETULT: in getSelectableIntSetCC()
1598 case ISD::SETUGE: in getSelectableIntSetCC()
1600 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getSelectableIntSetCC()
1604 case ISD::SETLE: in getSelectableIntSetCC()
1605 case ISD::SETGT: in getSelectableIntSetCC()
1607 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getSelectableIntSetCC()
1611 case ISD::SETULE: in getSelectableIntSetCC()
1612 case ISD::SETUGT: in getSelectableIntSetCC()
1614 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getSelectableIntSetCC()
1628 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC, in FPCCToA64CC()
1635 case ISD::SETEQ: in FPCCToA64CC()
1636 case ISD::SETOEQ: CondCode = A64CC::EQ; break; in FPCCToA64CC()
1637 case ISD::SETGT: in FPCCToA64CC()
1638 case ISD::SETOGT: CondCode = A64CC::GT; break; in FPCCToA64CC()
1639 case ISD::SETGE: in FPCCToA64CC()
1640 case ISD::SETOGE: CondCode = A64CC::GE; break; in FPCCToA64CC()
1641 case ISD::SETOLT: CondCode = A64CC::MI; break; in FPCCToA64CC()
1642 case ISD::SETOLE: CondCode = A64CC::LS; break; in FPCCToA64CC()
1643 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break; in FPCCToA64CC()
1644 case ISD::SETO: CondCode = A64CC::VC; break; in FPCCToA64CC()
1645 case ISD::SETUO: CondCode = A64CC::VS; break; in FPCCToA64CC()
1646 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break; in FPCCToA64CC()
1647 case ISD::SETUGT: CondCode = A64CC::HI; break; in FPCCToA64CC()
1648 case ISD::SETUGE: CondCode = A64CC::PL; break; in FPCCToA64CC()
1649 case ISD::SETLT: in FPCCToA64CC()
1650 case ISD::SETULT: CondCode = A64CC::LT; break; in FPCCToA64CC()
1651 case ISD::SETLE: in FPCCToA64CC()
1652 case ISD::SETULE: CondCode = A64CC::LE; break; in FPCCToA64CC()
1653 case ISD::SETNE: in FPCCToA64CC()
1654 case ISD::SETUNE: CondCode = A64CC::NE; break; in FPCCToA64CC()
1690 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit, in LowerBRCOND()
1695 DAG.getCondCode(ISD::SETNE)); in LowerBRCOND()
1707 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
1721 CC = ISD::SETNE; in LowerBR_CC()
1875 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr, in LowerGlobalAddressELF()
1922 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef, in LowerGlobalAddressELF()
2060 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff); in LowerGlobalTLSAddress()
2103 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
2114 CC = ISD::SETNE; in LowerSELECT_CC()
2162 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit, in LowerSELECT()
2166 DAG.getCondCode(ISD::SETNE)); in LowerSELECT()
2179 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
2266 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, in LowerVASTART()
2270 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop, in LowerVASTART()
2282 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, in LowerVASTART()
2286 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop, in LowerVASTART()
2295 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, in LowerVASTART()
2302 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, in LowerVASTART()
2308 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0], in LowerVASTART()
2316 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128); in LowerOperation()
2317 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128); in LowerOperation()
2318 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128); in LowerOperation()
2319 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128); in LowerOperation()
2320 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true); in LowerOperation()
2321 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false); in LowerOperation()
2322 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true); in LowerOperation()
2323 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false); in LowerOperation()
2324 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); in LowerOperation()
2325 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
2327 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
2328 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
2329 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
2330 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG); in LowerOperation()
2331 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
2332 case ISD::JumpTable: return LowerJumpTable(Op, DAG); in LowerOperation()
2333 case ISD::SELECT: return LowerSELECT(Op, DAG); in LowerOperation()
2334 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
2335 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
2336 case ISD::VACOPY: return LowerVACOPY(Op, DAG); in LowerOperation()
2337 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
2365 if (Shift.getOpcode() != ISD::SRL) in PerformANDCombine()
2405 SDValue Chain = AtomicNode->getOpcode() == ISD::ATOMIC_LOAD ? in PerformATOMIC_FENCECombine()
2411 SDValue Op = DAG.getAtomic(ISD::ATOMIC_LOAD, DL, AtomicNode->getMemoryVT(), in PerformATOMIC_FENCECombine()
2418 if (AtomicNode->getOpcode() == ISD::ATOMIC_LOAD) in PerformATOMIC_FENCECombine()
2432 if (FenceOp.getOpcode() != ISD::ATOMIC_FENCE) in PerformATOMIC_STORECombine()
2444 return DAG.getAtomic(ISD::ATOMIC_STORE, DL, AtomicNode->getMemoryVT(), in PerformATOMIC_STORECombine()
2475 if (MaskedVal.getOpcode() == ISD::SHL && in getLSBForBFI()
2479 } else if (MaskedVal.getOpcode() == ISD::SRL && in getLSBForBFI()
2486 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal, in getLSBForBFI()
2491 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal, in getLSBForBFI()
2504 if (N.getOpcode() == ISD::ZERO_EXTEND) { in findMaskedBFI()
2509 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) { in findMaskedBFI()
2536 assert(N->getOpcode() == ISD::OR && "Unexpected root"); in tryCombineToBFI()
2541 if (LHS.getOpcode() != ISD::AND) in tryCombineToBFI()
2553 if (RHS.getOpcode() != ISD::AND) in tryCombineToBFI()
2595 return DAG.getNode(ISD::AND, DL, VT, BFI, in tryCombineToBFI()
2631 if (PossExtraMask.getOpcode() != ISD::AND || in tryCombineToLargerBFI()
2649 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal); in tryCombineToLargerBFI()
2650 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal); in tryCombineToLargerBFI()
2665 return DAG.getNode(ISD::AND, DL, VT, BFI, in tryCombineToLargerBFI()
2673 if (N.getOpcode() == ISD::SHL) in findEXTRHalf()
2675 else if (N.getOpcode() == ISD::SRL) in findEXTRHalf()
2699 assert(N->getOpcode() == ISD::OR && "Unexpected root"); in tryCombineToEXTR()
2782 if (Shift.getOpcode() != ISD::SHL) in PerformSRACombine()
2806 case ISD::AND: return PerformANDCombine(N, DCI); in PerformDAGCombine()
2807 case ISD::ATOMIC_FENCE: return PerformATOMIC_FENCECombine(N, DCI); in PerformDAGCombine()
2808 case ISD::ATOMIC_STORE: return PerformATOMIC_STORECombine(N, DCI); in PerformDAGCombine()
2809 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); in PerformDAGCombine()
2810 case ISD::SRA: return PerformSRACombine(N, DCI); in PerformDAGCombine()