Lines Matching refs:DestReg
654 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
656 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
660 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
665 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
675 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
677 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
695 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
697 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
700 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
702 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
704 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
706 else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
709 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
711 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
713 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
722 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
730 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); in copyPhysReg()
745 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
945 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
964 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
968 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
975 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
982 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
983 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
984 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
985 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
992 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
996 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1006 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1017 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1018 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1026 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1034 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1035 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1036 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1037 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1038 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1039 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1050 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1051 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1052 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1053 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1054 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1055 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1056 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1057 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1058 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1059 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1247 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
1254 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1264 DestReg) in reMaterialize()
1776 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate() argument
1794 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitARMRegPlusImmediate()
1798 BaseReg = DestReg; in emitARMRegPlusImmediate()