Lines Matching refs:SrcReg
654 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
657 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
661 .addReg(SrcReg, getKillRegState(KillSrc)))); in copyPhysReg()
666 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
675 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
677 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
682 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
684 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
695 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
697 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
700 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
702 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
704 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
706 else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
709 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
711 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
713 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
722 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
731 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); in copyPhysReg()
747 Mov->addRegisterKilled(SrcReg, TRI); in copyPhysReg()
764 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
783 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
787 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
795 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
802 MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
803 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
813 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
817 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
830 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
837 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
838 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
839 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
851 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
858 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
859 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
860 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
861 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
872 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
873 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
874 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
875 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
876 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
877 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
878 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
879 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1947 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
1953 SrcReg = MI->getOperand(0).getReg(); in analyzeCompare()
1960 SrcReg = MI->getOperand(0).getReg(); in analyzeCompare()
1967 SrcReg = MI->getOperand(0).getReg(); in analyzeCompare()
1981 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, in isSuitableForMask() argument
1988 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) in isSuitableForMask()
2030 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, in isRedundantFlagInstr() argument
2037 ((OI->getOperand(1).getReg() == SrcReg && in isRedundantFlagInstr()
2040 OI->getOperand(2).getReg() == SrcReg))) in isRedundantFlagInstr()
2047 OI->getOperand(1).getReg() == SrcReg && in isRedundantFlagInstr()
2061 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
2065 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); in optimizeCompareInstr()
2070 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { in optimizeCompareInstr()
2072 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), in optimizeCompareInstr()
2076 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || in optimizeCompareInstr()
2126 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
2220 Sub->getOperand(2).getReg() == SrcReg) in optimizeCompareInstr()
3822 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
3839 SrcReg = MI->getOperand(1).getReg(); in setExecutionDomain()
3847 .addReg(SrcReg) in setExecutionDomain()
3848 .addReg(SrcReg)); in setExecutionDomain()
3857 SrcReg = MI->getOperand(1).getReg(); in setExecutionDomain()
3862 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); in setExecutionDomain()
3874 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
3883 SrcReg = MI->getOperand(1).getReg(); in setExecutionDomain()
3899 .addReg(SrcReg) in setExecutionDomain()
3916 SrcReg = MI->getOperand(1).getReg(); in setExecutionDomain()
3920 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); in setExecutionDomain()
3941 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
3978 NewMIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
3997 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()