388   unsigned DstReg = MI.getOperand(OpIdx++).getReg();  in ExpandVLD()  local
390   GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandVLD()
428   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
516   unsigned DstReg = 0;  in ExpandLaneOp()  local
520     DstReg = MI.getOperand(OpIdx++).getReg();  in ExpandLaneOp()
521     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandLaneOp()
570     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
617   unsigned DstReg = MI.getOperand(0).getReg();  in ExpandMOV32BitImm()  local
626     LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);  in ExpandMOV32BitImm()
628       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
629       .addReg(DstReg);  in ExpandMOV32BitImm()
656   LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);  in ExpandMOV32BitImm()
658     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
659     .addReg(DstReg);  in ExpandMOV32BitImm()
865       unsigned DstReg = MI.getOperand(0).getReg();  in ExpandMI()  local
869                                TII->get(NewLdOpc), DstReg)  in ExpandMI()
874         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
875         .addReg(DstReg)  in ExpandMI()
889       unsigned DstReg = MI.getOperand(0).getReg();  in ExpandMI()  local
906                                          TII->get(LO16Opc), DstReg)  in ExpandMI()
910                                          TII->get(HI16Opc), DstReg)  in ExpandMI()
911         .addReg(DstReg)  in ExpandMI()
922         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
923         .addReg(DstReg).addImm(LabelId);  in ExpandMI()
949       unsigned DstReg = MI.getOperand(OpIdx++).getReg();  in ExpandMI()  local
959       unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);  in ExpandMI()
960       unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);  in ExpandMI()
965       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()