Lines Matching refs:getOperand
78 const MachineOperand &MO = OldMI.getOperand(i); in TransferImpOps()
387 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
417 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
423 MachineOperand MO = MI.getOperand(SrcOpIdx); in ExpandVLD()
452 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
455 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
456 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
459 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
461 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); in ExpandVST()
462 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); in ExpandVST()
463 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); in ExpandVST()
475 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
476 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
505 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); in ExpandLaneOp()
519 DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandLaneOp()
520 DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandLaneOp()
532 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
535 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
536 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
539 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
542 MachineOperand MO = MI.getOperand(OpIdx++); in ExpandLaneOp()
562 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
563 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
588 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
590 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
592 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); in ExpandVTBL()
593 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); in ExpandVTBL()
599 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
602 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
603 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
617 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMOV32BitImm()
618 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMOV32BitImm()
620 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); in ExpandMOV32BitImm()
694 MI.getOperand(1).getReg()) in ExpandMI()
695 .addReg(MI.getOperand(2).getReg(), in ExpandMI()
696 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
697 .addImm(MI.getOperand(3).getImm()) // 'pred' in ExpandMI()
698 .addReg(MI.getOperand(4).getReg()); in ExpandMI()
707 MI.getOperand(1).getReg()) in ExpandMI()
708 .addReg(MI.getOperand(2).getReg(), in ExpandMI()
709 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
710 .addImm(MI.getOperand(3).getImm()) // 'pred' in ExpandMI()
711 .addReg(MI.getOperand(4).getReg()) in ExpandMI()
719 (MI.getOperand(1).getReg())) in ExpandMI()
720 .addReg(MI.getOperand(2).getReg(), in ExpandMI()
721 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
722 .addImm(MI.getOperand(3).getImm()) in ExpandMI()
723 .addImm(MI.getOperand(4).getImm()) // 'pred' in ExpandMI()
724 .addReg(MI.getOperand(5).getReg()) in ExpandMI()
733 (MI.getOperand(1).getReg())) in ExpandMI()
734 .addReg(MI.getOperand(2).getReg(), in ExpandMI()
735 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
736 .addReg(MI.getOperand(3).getReg(), in ExpandMI()
737 getKillRegState(MI.getOperand(3).isKill())) in ExpandMI()
738 .addImm(MI.getOperand(4).getImm()) in ExpandMI()
739 .addImm(MI.getOperand(5).getImm()) // 'pred' in ExpandMI()
740 .addReg(MI.getOperand(6).getReg()) in ExpandMI()
748 MI.getOperand(1).getReg()) in ExpandMI()
749 .addImm(MI.getOperand(2).getImm()) in ExpandMI()
750 .addImm(MI.getOperand(3).getImm()) // 'pred' in ExpandMI()
751 .addReg(MI.getOperand(4).getReg()); in ExpandMI()
760 MI.getOperand(1).getReg()) in ExpandMI()
761 .addImm(MI.getOperand(2).getImm()) in ExpandMI()
762 .addImm(MI.getOperand(3).getImm()) // 'pred' in ExpandMI()
763 .addReg(MI.getOperand(4).getReg()) in ExpandMI()
771 MI.getOperand(1).getReg()) in ExpandMI()
772 .addImm(MI.getOperand(2).getImm()) in ExpandMI()
773 .addImm(MI.getOperand(3).getImm()) // 'pred' in ExpandMI()
774 .addReg(MI.getOperand(4).getReg()) in ExpandMI()
828 MI.getOperand(0).getReg()) in ExpandMI()
829 .addOperand(MI.getOperand(1)) in ExpandMI()
841 MI.getOperand(0).getReg()) in ExpandMI()
842 .addOperand(MI.getOperand(1)) in ExpandMI()
865 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMI()
866 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMI()
870 .addOperand(MI.getOperand(1))); in ExpandMI()
876 .addOperand(MI.getOperand(2)); in ExpandMI()
889 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMI()
890 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMI()
891 const MachineOperand &MO1 = MI.getOperand(1); in ExpandMI()
948 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandMI()
949 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandMI()
952 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
955 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
956 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
979 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); in ExpandMI()
980 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); in ExpandMI()
983 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
986 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
987 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1009 unsigned SrcReg = MI.getOperand(1).getReg(); in ExpandMI()
1016 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1022 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1023 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()