Lines Matching refs:v8i16
1039 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1334 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
2007 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2049 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
3101 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3104 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3135 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3136 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3150 v8i8, v8i16, OpNode>;
3167 v8i8, v8i16, IntOp>;
3181 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3182 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3213 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3215 v8i16, v8i16, OpNode, Commutable>;
3224 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3262 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3264 v8i16, v8i16, IntOp, Commutable>;
3283 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3285 v8i16, v8i16, IntOp>;
3299 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3300 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3373 v8i8, v8i16, IntOp, Commutable>;
3389 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3391 v8i16, v8i8, OpNode, Commutable>;
3413 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3415 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3455 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3457 v8i16, v8i8, IntOp, Commutable>;
3464 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3466 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3481 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3483 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3510 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3511 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3524 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3525 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3549 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3550 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3571 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3572 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3584 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3585 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3626 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3627 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3634 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3635 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3661 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3662 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3663 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3684 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3685 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3686 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3720 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3721 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3757 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3758 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3796 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3797 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3836 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3837 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3872 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3873 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3889 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3890 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3910 v8i8, v8i16, shr_imm8, OpNode> {
3992 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3993 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3994 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4018 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4019 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4021 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4040 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4041 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4043 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4061 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4091 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4092 (mul (v8i16 QPR:$src2),
4093 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4094 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4149 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4150 (mul (v8i16 QPR:$src2),
4151 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4152 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4368 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4419 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4458 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4538 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4539 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4797 v8i16, v8i8, imm8, NEONvshlli>;
4921 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4938 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5004 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5088 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5096 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5158 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5159 (v8i16 (INSERT_SUBREG QPR:$src1,
5201 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5202 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5226 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5273 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5292 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5293 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5323 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5402 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5423 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5451 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5505 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5718 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5723 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5727 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5728 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5729 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5730 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5731 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5734 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5739 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5744 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5756 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
5875 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16