1104     unsigned EvenReg = MI->getOperand(0).getReg();  in FixInvalidRegPairOp()  local
1106     unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);  in FixInvalidRegPairOp()
1110     bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();  in FixInvalidRegPairOp()
1142           .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))  in FixInvalidRegPairOp()
1149           .addReg(EvenReg,  in FixInvalidRegPairOp()
1171           (TRI->regsOverlap(EvenReg, BaseReg))) {  in FixInvalidRegPairOp()
1179                       EvenReg, EvenDeadKill, false,  in FixInvalidRegPairOp()
1183         if (OddReg == EvenReg && EvenDeadKill) {  in FixInvalidRegPairOp()
1191         if (EvenReg == BaseReg)  in FixInvalidRegPairOp()
1194                       EvenReg, EvenDeadKill, EvenUndef,  in FixInvalidRegPairOp()
1465                           unsigned &NewOpc, unsigned &EvenReg,
1561                                           unsigned &NewOpc, unsigned &EvenReg,  in CanFormLdStDWord()  argument
1620   EvenReg = Op0->getOperand(0).getReg();  in CanFormLdStDWord()
1622   if (EvenReg == OddReg)  in CanFormLdStDWord()
1723         unsigned EvenReg = 0, OddReg = 0;  in RescheduleOps()  local
1731                                              EvenReg, OddReg, BaseReg,  in RescheduleOps()
1738           MRI->constrainRegClass(EvenReg, TRC);  in RescheduleOps()
1744               .addReg(EvenReg, RegState::Define)  in RescheduleOps()
1758               .addReg(EvenReg)  in RescheduleOps()
1775           MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);  in RescheduleOps()
1776           MRI->setRegAllocationHint(OddReg,  ARMRI::RegPairOdd, EvenReg);  in RescheduleOps()