349   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))  in MergeOps()  local
353     MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)  in MergeOps()
358     MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);  in MergeOps()
777   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))  in MergeBaseUpdateLSMultiple()  local
784     MIB.addOperand(MI->getOperand(OpNum));  in MergeBaseUpdateLSMultiple()
787   MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());  in MergeBaseUpdateLSMultiple()
1082     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),  in InsertLDR_STR()  local
1086     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1088     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),  in InsertLDR_STR()  local
1092     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1743             MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)  in RescheduleOps()  local
1751               MIB.addReg(0);  in RescheduleOps()
1752             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
1753             concatenateMemOperands(MIB, Op0, Op1);  in RescheduleOps()
1754             DEBUG(dbgs() << "Formed " << *MIB << "\n");  in RescheduleOps()
1757             MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)  in RescheduleOps()  local
1765               MIB.addReg(0);  in RescheduleOps()
1766             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
1767             concatenateMemOperands(MIB, Op0, Op1);  in RescheduleOps()
1768             DEBUG(dbgs() << "Formed " << *MIB << "\n");  in RescheduleOps()