93                               unsigned DestReg, unsigned BaseReg,  in emitThumbRegPlusImmInReg()  argument
100                   (BaseReg != 0 && !isARMLowRegister(BaseReg));  in emitThumbRegPlusImmInReg()
112       assert(BaseReg == ARM::SP && "Unexpected!");  in emitThumbRegPlusImmInReg()
135       MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);  in emitThumbRegPlusImmInReg()
137       MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);  in emitThumbRegPlusImmInReg()
170                                      unsigned DestReg, unsigned BaseReg,  in emitThumbRegPlusImmediate()  argument
186   if (DestReg == BaseReg && BaseReg == ARM::SP) {  in emitThumbRegPlusImmediate()
192   } else if (!isSub && BaseReg == ARM::SP) {  in emitThumbRegPlusImmediate()
208     if (DestReg != BaseReg)  in emitThumbRegPlusImmediate()
230                              DestReg, BaseReg, NumBytes, true,  in emitThumbRegPlusImmediate()
236     if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {  in emitThumbRegPlusImmediate()
245       AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));  in emitThumbRegPlusImmediate()
248         .addReg(BaseReg, RegState::Kill))  in emitThumbRegPlusImmediate()
251     BaseReg = DestReg;  in emitThumbRegPlusImmediate()
268       bool isKill = BaseReg != ARM::SP;  in emitThumbRegPlusImmediate()
272       MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);  in emitThumbRegPlusImmediate()
276       BaseReg = DestReg;  in emitThumbRegPlusImmediate()
489                                       unsigned BaseReg, int64_t Offset) const {  in resolveFrameIndex()  argument
498   bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);  in resolveFrameIndex()