Lines Matching refs:Rd

37   // Rd - 64-bit registers.
38   class Rd<bits<5> num, string n, list<Register> subregs> :
103   def D0  : Rd< 0,  "r1:0",  [R0,  R1]>, DwarfRegNum<[32]>;
104   def D1  : Rd< 2,  "r3:2",  [R2,  R3]>, DwarfRegNum<[34]>;
105   def D2  : Rd< 4,  "r5:4",  [R4,  R5]>, DwarfRegNum<[36]>;
106   def D3  : Rd< 6,  "r7:6",  [R6,  R7]>, DwarfRegNum<[38]>;
107   def D4  : Rd< 8,  "r9:8",  [R8,  R9]>, DwarfRegNum<[40]>;
108   def D5  : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
109   def D6  : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
110   def D7  : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
111   def D8  : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
112   def D9  : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
113   def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
114   def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
115   def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
116   def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
117   def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
118   def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;