Lines Matching refs:operand
17 // source operands or one register source operand and one immediate operand.
28 , 1 // first operand read after one cycle
29 , 1 ]>, // second operand read after one cycle
32 // register source operands or one register source operand and one immediate
33 // operand. The instruction takes one cycle to execute in each of the
43 , 1 // first operand read after one cycle
44 , 1 ]>, // second operand read after one cycle
58 , 1 // first operand read after one cycle
59 , 1 ]>, // second operand read after one cycle
62 // source operands or one register source operand and one immediate operand.
73 , 1 // first operand read after one cycle
74 , 1 ]>, // second operand read after one cycle
76 // Branch instruction with one source operand register. The instruction takes
77 // one cycle to execute in each of the pipeline stages. The source operand is
85 [ 1 ]>, // first operand read after one cycle
87 // Conditional branch instruction with two source operand registers. The
96 [ 1 // first operand read after one cycle
97 , 1 ]>, // second operand read after one cycle
100 // operand register. The instruction takes one cycle to execute in each of
101 // the pipeline stages. The source operand is read during the decode stage
110 , 1 ]>, // first operand read after one cycle
112 // Cache control instruction with two source operand registers. The
122 [ 1 // first operand read after one cycle
123 , 1 ]>, // second operand read after one cycle
126 // operand registers. The instruction takes one cycle to execute in each of
137 , 1 // first operand read after one cycle
138 , 1 ]>, // second operand read after one cycle
141 // source operand registers. The instruction takes one cycle to execute in
152 , 1 // first operand read after one cycle
153 , 1 ]>, // second operand read after one cycle
156 // register and one source operand register. The instruction takes one cycle
167 , 1 ]>, // first operand read after one cycle
170 // register and one source operand register. The instruction takes one cycle
181 , 1 ]>, // first operand read after one cycle
184 // one source operand register. The instruction takes one cycle to execute in
195 , 1 ]>, // first operand read after one cycle
198 // two source operand registers. The instruction takes one cycle to execute
208 , 1 // first operand read after one cycle
209 , 1 ]>, // second operand read after one cycle
211 // FSL get instruction with one register or immediate source operand and one
213 // of the pipeline stages. The one source operand is read during the decode
222 , 1 ]>, // first operand read after one cycle
225 // register source operand and one immediate operand. There is no result
235 [ 1 // first operand read after one cycle
236 , 1 ]>, // second operand read after one cycle
239 // register source operands and one immediate operand. There is no result
249 [ 1 // first operand read after one cycle
250 , 1 // second operand read after one cycle
251 , 1 ]>, // third operand read after one cycle
254 // register source operands or one register source operand and one immediate
255 // operand. The instruction takes one cycle to execute in each of the
265 , 1 // second operand read after one cycle
266 , 1 ]> // third operand read after one cycle