36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,  in MipsDisassemblerBase()  argument
38     MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}  in MipsDisassemblerBase()
55   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,  in MipsDisassembler()  argument
57     MipsDisassemblerBase(STI, Info, bigEndian) {}  in MipsDisassembler()
74   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,  in Mips64Disassembler()  argument
76     MipsDisassemblerBase(STI, Info, bigEndian) {}  in Mips64Disassembler()
198                        const MCSubtargetInfo &STI) {  in createMipsDisassembler()  argument
199   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);  in createMipsDisassembler()
204                        const MCSubtargetInfo &STI) {  in createMipselDisassembler()  argument
205   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);  in createMipselDisassembler()
210                        const MCSubtargetInfo &STI) {  in createMips64Disassembler()  argument
211   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);  in createMips64Disassembler()
216                        const MCSubtargetInfo &STI) {  in createMips64elDisassembler()  argument
217   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);  in createMips64elDisassembler()
284                              this, STI);  in getInstruction()
309                              this, STI);  in getInstruction()
316                              this, STI);  in getInstruction()