108   unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
110   unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
111   unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
112   unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
113   unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
173                                                unsigned OpNo) const {  in getJumpTargetOpValue()
174   MachineOperand MO = MI.getOperand(OpNo);  in getJumpTargetOpValue()
187                                                  unsigned OpNo) const {  in getBranchTargetOpValue()
188   MachineOperand MO = MI.getOperand(OpNo);  in getBranchTargetOpValue()
194                                          unsigned OpNo) const {  in getMemEncoding()
196   assert(MI.getOperand(OpNo).isReg());  in getMemEncoding()
197   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;  in getMemEncoding()
198   return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;  in getMemEncoding()
202                                              unsigned OpNo) const {  in getSizeExtEncoding()
204   return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;  in getSizeExtEncoding()
208                                              unsigned OpNo) const {  in getSizeInsEncoding()
210   return getMachineOpValue(MI, MI.getOperand(OpNo-1)) +  in getSizeInsEncoding()
211          getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;  in getSizeInsEncoding()