Lines Matching refs:ISD
37 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
41 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
42 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
43 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
44 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
45 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
46 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
47 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
51 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
52 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
54 setOperationAction(ISD::STORE, MVT::v4f32, Promote); in AMDGPUTargetLowering()
55 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
57 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
58 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
60 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
61 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
63 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
64 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
65 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
73 const SmallVectorImpl<ISD::InputArg> &Ins) const { in AnalyzeFormalArguments()
82 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
101 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
102 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
103 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
104 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
106 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
107 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
147 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
157 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), in LowerIntrinsicIABS()
169 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, in LowerIntrinsicLRP()
172 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, in LowerIntrinsicLRP()
174 return DAG.getNode(ISD::FADD, DL, VT, in LowerIntrinsicLRP()
175 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), in LowerIntrinsicLRP()
196 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerMinMax()
198 case ISD::SETOEQ: in LowerMinMax()
199 case ISD::SETONE: in LowerMinMax()
200 case ISD::SETUNE: in LowerMinMax()
201 case ISD::SETNE: in LowerMinMax()
202 case ISD::SETUEQ: in LowerMinMax()
203 case ISD::SETEQ: in LowerMinMax()
204 case ISD::SETFALSE: in LowerMinMax()
205 case ISD::SETFALSE2: in LowerMinMax()
206 case ISD::SETTRUE: in LowerMinMax()
207 case ISD::SETTRUE2: in LowerMinMax()
208 case ISD::SETUO: in LowerMinMax()
209 case ISD::SETO: in LowerMinMax()
211 case ISD::SETULE: in LowerMinMax()
212 case ISD::SETULT: in LowerMinMax()
213 case ISD::SETOLE: in LowerMinMax()
214 case ISD::SETOLT: in LowerMinMax()
215 case ISD::SETLE: in LowerMinMax()
216 case ISD::SETLT: { in LowerMinMax()
222 case ISD::SETGT: in LowerMinMax()
223 case ISD::SETGE: in LowerMinMax()
224 case ISD::SETUGE: in LowerMinMax()
225 case ISD::SETOGE: in LowerMinMax()
226 case ISD::SETUGT: in LowerMinMax()
227 case ISD::SETOGT: { in LowerMinMax()
233 case ISD::SETCC_INVALID: in LowerMinMax()
256 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den); in LowerUDIVREM()
259 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
262 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), in LowerUDIVREM()
268 ISD::SETEQ); in LowerUDIVREM()
271 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
274 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E); in LowerUDIVREM()
277 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); in LowerUDIVREM()
282 ISD::SETEQ); in LowerUDIVREM()
284 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
287 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den); in LowerUDIVREM()
290 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder); in LowerUDIVREM()
296 ISD::SETGE); in LowerUDIVREM()
302 ISD::SETGE); in LowerUDIVREM()
304 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, in LowerUDIVREM()
310 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient, in LowerUDIVREM()
314 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient, in LowerUDIVREM()
319 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
323 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
328 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den); in LowerUDIVREM()
331 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den); in LowerUDIVREM()
335 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
339 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()