Lines Matching refs:Op
92 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) in LowerOperation() argument
94 switch (Op.getOpcode()) { in LowerOperation()
96 Op.getNode()->dump(); in LowerOperation()
101 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
102 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
103 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
104 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
106 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
107 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
109 return Op; in LowerOperation()
112 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, in LowerINTRINSIC_WO_CHAIN() argument
114 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); in LowerINTRINSIC_WO_CHAIN()
115 DebugLoc DL = Op.getDebugLoc(); in LowerINTRINSIC_WO_CHAIN()
116 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN()
119 default: return Op; in LowerINTRINSIC_WO_CHAIN()
121 return LowerIntrinsicIABS(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
125 return LowerIntrinsicLRP(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
129 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
130 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
132 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
133 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
135 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
136 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
138 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
139 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
141 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
142 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
144 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
145 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
147 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
152 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, in LowerIntrinsicIABS() argument
155 DebugLoc DL = Op.getDebugLoc(); in LowerIntrinsicIABS()
156 EVT VT = Op.getValueType(); in LowerIntrinsicIABS()
158 Op.getOperand(1)); in LowerIntrinsicIABS()
160 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1)); in LowerIntrinsicIABS()
165 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, in LowerIntrinsicLRP() argument
167 DebugLoc DL = Op.getDebugLoc(); in LowerIntrinsicLRP()
168 EVT VT = Op.getValueType(); in LowerIntrinsicLRP()
171 Op.getOperand(1)); in LowerIntrinsicLRP()
173 Op.getOperand(3)); in LowerIntrinsicLRP()
175 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), in LowerIntrinsicLRP()
180 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op, in LowerMinMax() argument
182 DebugLoc DL = Op.getDebugLoc(); in LowerMinMax()
183 EVT VT = Op.getValueType(); in LowerMinMax()
185 SDValue LHS = Op.getOperand(0); in LowerMinMax()
186 SDValue RHS = Op.getOperand(1); in LowerMinMax()
187 SDValue True = Op.getOperand(2); in LowerMinMax()
188 SDValue False = Op.getOperand(3); in LowerMinMax()
189 SDValue CC = Op.getOperand(4); in LowerMinMax()
236 return Op; in LowerMinMax()
241 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, in LowerUDIVREM() argument
243 DebugLoc DL = Op.getDebugLoc(); in LowerUDIVREM()
244 EVT VT = Op.getValueType(); in LowerUDIVREM()
246 SDValue Num = Op.getOperand(0); in LowerUDIVREM()
247 SDValue Den = Op.getOperand(1); in LowerUDIVREM()
350 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const { in isHWTrueValue()
351 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) { in isHWTrueValue()
354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { in isHWTrueValue()
360 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const { in isHWFalseValue()
361 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) { in isHWFalseValue()
364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { in isHWFalseValue()