Lines Matching refs:ISD
31 setOperationAction(ISD::MUL, MVT::i64, Expand); in R600TargetLowering()
38 setOperationAction(ISD::FADD, MVT::v4f32, Expand); in R600TargetLowering()
39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand); in R600TargetLowering()
40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in R600TargetLowering()
41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); in R600TargetLowering()
43 setOperationAction(ISD::ADD, MVT::v4i32, Expand); in R600TargetLowering()
44 setOperationAction(ISD::AND, MVT::v4i32, Expand); in R600TargetLowering()
45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand); in R600TargetLowering()
46 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand); in R600TargetLowering()
47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand); in R600TargetLowering()
48 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand); in R600TargetLowering()
49 setOperationAction(ISD::UDIV, MVT::v4i32, Expand); in R600TargetLowering()
50 setOperationAction(ISD::UREM, MVT::v4i32, Expand); in R600TargetLowering()
51 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
53 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in R600TargetLowering()
54 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in R600TargetLowering()
56 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
58 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in R600TargetLowering()
59 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in R600TargetLowering()
60 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom); in R600TargetLowering()
61 setOperationAction(ISD::FPOW, MVT::f32, Custom); in R600TargetLowering()
63 setOperationAction(ISD::ROTL, MVT::i32, Custom); in R600TargetLowering()
65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
68 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
69 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
70 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); in R600TargetLowering()
72 setOperationAction(ISD::SELECT, MVT::i32, Custom); in R600TargetLowering()
73 setOperationAction(ISD::SELECT, MVT::f32, Custom); in R600TargetLowering()
76 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
77 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
79 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom); in R600TargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom); in R600TargetLowering()
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); in R600TargetLowering()
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom); in R600TargetLowering()
83 setOperationAction(ISD::STORE, MVT::i8, Custom); in R600TargetLowering()
84 setOperationAction(ISD::STORE, MVT::i32, Custom); in R600TargetLowering()
85 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in R600TargetLowering()
86 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in R600TargetLowering()
88 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
89 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
90 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
92 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
93 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
94 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
95 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
314 case ISD::ROTL: return LowerROTL(Op, DAG); in LowerOperation()
315 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
316 case ISD::SELECT: return LowerSELECT(Op, DAG); in LowerOperation()
317 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
318 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
319 case ISD::FPOW: return LowerFPOW(Op, DAG); in LowerOperation()
320 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); in LowerOperation()
321 case ISD::INTRINSIC_VOID: { in LowerOperation()
355 case ISD::INTRINSIC_WO_CHAIN: { in LowerOperation()
448 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG)); in ReplaceNodeResults()
450 case ISD::LOAD: { in ReplaceNodeResults()
459 case ISD::STORE: in ReplaceNodeResults()
468 ISD::SETCC, in LowerFPTOUINT()
472 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
513 DAG.getNode(ISD::SUB, DL, VT, in LowerROTL()
555 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
557 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32)); in LowerSELECT_CC()
563 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
578 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
584 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
585 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
588 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
592 case ISD::SETONE: in LowerSELECT_CC()
593 case ISD::SETUNE: in LowerSELECT_CC()
594 case ISD::SETNE: in LowerSELECT_CC()
595 case ISD::SETULE: in LowerSELECT_CC()
596 case ISD::SETULT: in LowerSELECT_CC()
597 case ISD::SETOLE: in LowerSELECT_CC()
598 case ISD::SETOLT: in LowerSELECT_CC()
599 case ISD::SETLE: in LowerSELECT_CC()
600 case ISD::SETLT: in LowerSELECT_CC()
601 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
609 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
613 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
640 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
642 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
645 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
649 return DAG.getNode(ISD::SELECT_CC, in LowerSELECT()
656 DAG.getCondCode(ISD::SETNE)); in LowerSELECT()
681 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
725 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
762 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerSTORE()
764 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, in LowerSTORE()
771 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT); in LowerSTORE()
774 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value); in LowerSTORE()
846 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in LowerLOAD()
850 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4); in LowerLOAD()
854 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)), in LowerLOAD()
861 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
895 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerLOAD()
906 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4); in LowerLOAD()
925 SDValue LogBase = DAG.getNode(ISD::FLOG2, DL, VT, Op.getOperand(0)); in LowerFPOW()
926 SDValue MulLogBase = DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), LogBase); in LowerFPOW()
927 return DAG.getNode(ISD::FEXP2, DL, VT, MulLogBase); in LowerFPOW()
937 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
959 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(), in LowerFormalArguments()
984 case ISD::FP_ROUND: { in PerformDAGCombine()
986 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
987 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), N->getValueType(0), in PerformDAGCombine()
998 case ISD::FP_TO_SINT: { in PerformDAGCombine()
1000 if (FNeg.getOpcode() != ISD::FNEG) { in PerformDAGCombine()
1004 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1012 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N->getValueType(0), in PerformDAGCombine()
1023 case ISD::EXTRACT_VECTOR_ELT: { in PerformDAGCombine()
1025 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1031 if (Arg.getOpcode() == ISD::BITCAST && in PerformDAGCombine()
1032 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1035 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getVTList(), in PerformDAGCombine()
1041 case ISD::SELECT_CC: { in PerformDAGCombine()
1048 if (LHS.getOpcode() != ISD::SELECT_CC) { in PerformDAGCombine()
1055 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1065 case ISD::SETNE: return LHS; in PerformDAGCombine()
1066 case ISD::SETEQ: { in PerformDAGCombine()
1067 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()
1068 LHSCC = ISD::getSetCCInverse(LHSCC, in PerformDAGCombine()
1081 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
1113 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4); in PerformDAGCombine()