Lines Matching refs:BaseReg
489 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
492 if (BaseReg == X86::RIP || in emitMemModRMByte()
511 if (BaseReg != 0 && BaseReg != X86::RIP) in emitMemModRMByte()
512 BaseRegNo = getX86RegNum(BaseReg); in emitMemModRMByte()
522 (!Is64BitMode || BaseReg != 0)) { in emitMemModRMByte()
523 if (BaseReg == 0 || // [disp32] in X86-32 mode in emitMemModRMByte()
524 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode in emitMemModRMByte()
558 if (BaseReg == 0) { in emitMemModRMByte()
583 if (BaseReg == 0) { in emitMemModRMByte()
593 unsigned BaseRegNo = getX86RegNum(BaseReg); in emitMemModRMByte()
620 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
623 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
624 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
634 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
637 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
638 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
649 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
652 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
653 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()