Lines Matching refs:Mask
2659 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); in LowerCall() local
2660 assert(Mask && "Missing call preserved mask for calling convention"); in LowerCall()
2661 Ops.push_back(DAG.getRegisterMask(Mask)); in LowerCall()
3322 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, in isSequentialOrUndefInRange() argument
3325 if (!isUndefOrEqual(Mask[i], Low)) in isSequentialOrUndefInRange()
3333 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { in isPSHUFDMask() argument
3335 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); in isPSHUFDMask()
3337 return (Mask[0] < 2 && Mask[1] < 2); in isPSHUFDMask()
3343 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { in isPSHUFHWMask() argument
3348 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) in isPSHUFHWMask()
3353 if (!isUndefOrInRange(Mask[i], 4, 8)) in isPSHUFHWMask()
3358 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) in isPSHUFHWMask()
3363 if (!isUndefOrInRange(Mask[i], 12, 16)) in isPSHUFHWMask()
3372 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { in isPSHUFLWMask() argument
3377 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) in isPSHUFLWMask()
3382 if (!isUndefOrInRange(Mask[i], 0, 4)) in isPSHUFLWMask()
3387 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) in isPSHUFLWMask()
3392 if (!isUndefOrInRange(Mask[i], 8, 12)) in isPSHUFLWMask()
3401 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, in isPALIGNRMask() argument
3418 if (Mask[i+l] >= 0) in isPALIGNRMask()
3426 int Start = Mask[i+l]; in isPALIGNRMask()
3434 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) in isPALIGNRMask()
3449 int Idx = Mask[i+l]; in isPALIGNRMask()
3457 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) in isPALIGNRMask()
3474 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, in CommuteVectorShuffleMask() argument
3477 int idx = Mask[i]; in CommuteVectorShuffleMask()
3481 Mask[i] = idx + NumElems; in CommuteVectorShuffleMask()
3483 Mask[i] = idx - NumElems; in CommuteVectorShuffleMask()
3491 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256, in isSHUFPMask() argument
3525 int Idx = Mask[i+l]; in isSHUFPMask()
3532 if (NumElems != 8 || l == 0 || Mask[i] < 0) in isSHUFPMask()
3534 if (!isUndefOrEqual(Idx, Mask[i]+l)) in isSHUFPMask()
3544 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { in isMOVHLPSMask() argument
3554 return isUndefOrEqual(Mask[0], 6) && in isMOVHLPSMask()
3555 isUndefOrEqual(Mask[1], 7) && in isMOVHLPSMask()
3556 isUndefOrEqual(Mask[2], 2) && in isMOVHLPSMask()
3557 isUndefOrEqual(Mask[3], 3); in isMOVHLPSMask()
3563 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { in isMOVHLPS_v_undef_Mask() argument
3572 return isUndefOrEqual(Mask[0], 2) && in isMOVHLPS_v_undef_Mask()
3573 isUndefOrEqual(Mask[1], 3) && in isMOVHLPS_v_undef_Mask()
3574 isUndefOrEqual(Mask[2], 2) && in isMOVHLPS_v_undef_Mask()
3575 isUndefOrEqual(Mask[3], 3); in isMOVHLPS_v_undef_Mask()
3580 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { in isMOVLPMask() argument
3590 if (!isUndefOrEqual(Mask[i], i + NumElems)) in isMOVLPMask()
3594 if (!isUndefOrEqual(Mask[i], i)) in isMOVLPMask()
3602 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { in isMOVLHPSMask() argument
3612 if (!isUndefOrEqual(Mask[i], i)) in isMOVLHPSMask()
3616 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) in isMOVLHPSMask()
3634 ArrayRef<int> Mask = SVOp->getMask(); in Compact8x32ShuffleNode() local
3642 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i])) in Compact8x32ShuffleNode()
3644 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i])) in Compact8x32ShuffleNode()
3671 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, in isUNPCKLMask() argument
3691 int BitI = Mask[i]; in isUNPCKLMask()
3692 int BitI1 = Mask[i+1]; in isUNPCKLMask()
3710 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, in isUNPCKHMask() argument
3729 int BitI = Mask[i]; in isUNPCKHMask()
3730 int BitI1 = Mask[i+1]; in isUNPCKHMask()
3748 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { in isUNPCKL_v_undef_Mask() argument
3775 int BitI = Mask[i]; in isUNPCKL_v_undef_Mask()
3776 int BitI1 = Mask[i+1]; in isUNPCKL_v_undef_Mask()
3791 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { in isUNPCKH_v_undef_Mask() argument
3809 int BitI = Mask[i]; in isUNPCKH_v_undef_Mask()
3810 int BitI1 = Mask[i+1]; in isUNPCKH_v_undef_Mask()
3823 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { in isMOVLMask() argument
3831 if (!isUndefOrEqual(Mask[0], NumElts)) in isMOVLMask()
3835 if (!isUndefOrEqual(Mask[i], i)) in isMOVLMask()
3847 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { in isVPERM2X128Mask() argument
3859 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { in isVPERM2X128Mask()
3867 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { in isVPERM2X128Mask()
3907 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { in isVPERMILPMask() argument
3920 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) in isVPERMILPMask()
3925 if (Mask[i] < 0) in isVPERMILPMask()
3927 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) in isVPERMILPMask()
3938 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, in isCommutedMOVLMask() argument
3947 if (!isUndefOrEqual(Mask[0], 0)) in isCommutedMOVLMask()
3951 if (!(isUndefOrEqual(Mask[i], i+NumOps) || in isCommutedMOVLMask()
3952 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || in isCommutedMOVLMask()
3953 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) in isCommutedMOVLMask()
3962 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, in isMOVSHDUPMask() argument
3975 if (!isUndefOrEqual(Mask[i], i+1) || in isMOVSHDUPMask()
3976 !isUndefOrEqual(Mask[i+1], i+1)) in isMOVSHDUPMask()
3985 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, in isMOVSLDUPMask() argument
3998 if (!isUndefOrEqual(Mask[i], i) || in isMOVSLDUPMask()
3999 !isUndefOrEqual(Mask[i+1], i)) in isMOVSLDUPMask()
4008 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { in isMOVDDUPYMask() argument
4017 if (!isUndefOrEqual(Mask[i], 0)) in isMOVDDUPYMask()
4020 if (!isUndefOrEqual(Mask[i], NumElts/2)) in isMOVDDUPYMask()
4028 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { in isMOVDDUPMask() argument
4034 if (!isUndefOrEqual(Mask[i], i)) in isMOVDDUPMask()
4037 if (!isUndefOrEqual(Mask[e+i], i)) in isMOVDDUPMask()
4097 unsigned Mask = 0; in getShuffleSHUFImmediate() local
4103 Mask |= Elt << ShAmt; in getShuffleSHUFImmediate()
4106 return Mask; in getShuffleSHUFImmediate()
4119 unsigned Mask = 0; in getShufflePSHUFHWImmediate() local
4126 Mask |= Elt << (i * 2); in getShufflePSHUFHWImmediate()
4130 return Mask; in getShufflePSHUFHWImmediate()
4143 unsigned Mask = 0; in getShufflePSHUFLWImmediate() local
4150 Mask |= Elt << (i * 2); in getShufflePSHUFLWImmediate()
4154 return Mask; in getShufflePSHUFLWImmediate()
4226 unsigned Mask = 0; in getShuffleCLImmediate() local
4231 Mask |= Elt << (i*2); in getShuffleCLImmediate()
4234 return Mask; in getShuffleCLImmediate()
4272 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { in ShouldXformToMOVHLPS() argument
4278 if (!isUndefOrEqual(Mask[i], i+2)) in ShouldXformToMOVHLPS()
4281 if (!isUndefOrEqual(Mask[i], i+4)) in ShouldXformToMOVHLPS()
4329 ArrayRef<int> Mask, EVT VT) { in ShouldXformToMOVLP() argument
4345 if (!isUndefOrEqual(Mask[i], i)) in ShouldXformToMOVLP()
4348 if (!isUndefOrEqual(Mask[i], i+NumElems)) in ShouldXformToMOVLP()
4457 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { in NormalizeMask() argument
4459 if (Mask[i] > (int)NumElems) { in NormalizeMask()
4460 Mask[i] = NumElems; in NormalizeMask()
4470 SmallVector<int, 8> Mask; in getMOVL() local
4471 Mask.push_back(NumElems); in getMOVL()
4473 Mask.push_back(i); in getMOVL()
4474 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); in getMOVL()
4481 SmallVector<int, 8> Mask; in getUnpackl() local
4483 Mask.push_back(i); in getUnpackl()
4484 Mask.push_back(i + NumElems); in getUnpackl()
4486 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); in getUnpackl()
4493 SmallVector<int, 8> Mask; in getUnpackh() local
4495 Mask.push_back(i + Half); in getUnpackh()
4496 Mask.push_back(i + NumElems + Half); in getUnpackh()
4498 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); in getUnpackh()
4610 SmallVectorImpl<int> &Mask, bool &IsUnary) { in getTargetShuffleMask() argument
4618 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4621 DecodeUNPCKHMask(VT, Mask); in getTargetShuffleMask()
4624 DecodeUNPCKLMask(VT, Mask); in getTargetShuffleMask()
4627 DecodeMOVHLPSMask(NumElems, Mask); in getTargetShuffleMask()
4630 DecodeMOVLHPSMask(NumElems, Mask); in getTargetShuffleMask()
4634 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4639 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4644 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4649 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4654 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4662 Mask.push_back(NumElems); in getTargetShuffleMask()
4664 Mask.push_back(i); in getTargetShuffleMask()
4670 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); in getTargetShuffleMask()
4671 if (Mask.empty()) return false; in getTargetShuffleMask()
5041 SmallVector<int, 8> Mask; in LowerAsSplatVectorLoad() local
5043 Mask.push_back(EltNo); in LowerAsSplatVectorLoad()
5045 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); in LowerAsSplatVectorLoad()
5280 SmallVector<int, 8> Mask(NumElems, -1); in buildFromShuffleMostly() local
5321 Mask[i] = Idx; in buildFromShuffleMostly()
5323 Mask[i] = Idx + NumElems; in buildFromShuffleMostly()
5330 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]); in buildFromShuffleMostly()
5426 SmallVector<int, 4> Mask; in LowerBUILD_VECTOR() local
5427 Mask.push_back(Idx); in LowerBUILD_VECTOR()
5429 Mask.push_back(i); in LowerBUILD_VECTOR()
5431 &Mask[0]); in LowerBUILD_VECTOR()
6280 SmallVector<int, 16> Mask; in LowerVECTOR_SHUFFLE_256() local
6294 Mask.push_back(-1); in LowerVECTOR_SHUFFLE_256()
6325 Mask.push_back(Idx + OpNo * NumLaneElems); in LowerVECTOR_SHUFFLE_256()
6365 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); in LowerVECTOR_SHUFFLE_256()
6368 Mask.clear(); in LowerVECTOR_SHUFFLE_256()
6671 unsigned Mask = (1U << Shift) - 1; in LowerVectorIntExtend() local
6674 if ((i & Mask) != 0 && EltIdx != -1) in LowerVectorIntExtend()
6676 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift)) in LowerVectorIntExtend()
7047 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, in LowerVECTOR_SHUFFLE() local
7051 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); in LowerVECTOR_SHUFFLE()
7218 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; in LowerEXTRACT_VECTOR_ELT() local
7221 DAG.getUNDEF(VVT), Mask); in LowerEXTRACT_VECTOR_ELT()
7237 int Mask[2] = { 1, -1 }; in LowerEXTRACT_VECTOR_ELT() local
7240 DAG.getUNDEF(VVT), Mask); in LowerEXTRACT_VECTOR_ELT()
8433 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1}; in LowerZERO_EXTEND() local
8437 &Mask[0])); in LowerZERO_EXTEND()
8636 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, in LowerFABS() local
8645 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask))); in LowerFABS()
8647 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); in LowerFABS()
8670 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, in LowerFNEG() local
8679 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); in LowerFNEG()
8682 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); in LowerFNEG()
9361 const int Mask[] = { 1, 0, 3, 2 }; in LowerVSETCC() local
9362 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask); in LowerVSETCC()
11560 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); in LowerShift() local
11561 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); in LowerShift()
11562 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); in LowerShift()
11604 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); in LowerShift() local
11605 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); in LowerShift()
11606 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); in LowerShift()
12706 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, in isVectorClearMaskLegal() argument
12713 return (isMOVLMask(Mask, VT) || in isVectorClearMaskLegal()
12714 isCommutedMOVLMask(Mask, VT, true) || in isVectorClearMaskLegal()
12715 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) || in isVectorClearMaskLegal()
12716 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true)); in isVectorClearMaskLegal()
15891 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); in PerformSHLCombine() local
15893 Mask = Mask.shl(ShAmt); in PerformSHLCombine()
15894 if (Mask != 0) in PerformSHLCombine()
15896 N00, DAG.getConstant(Mask, VT)); in PerformSHLCombine()
16219 APInt Mask = APInt::getAllOnesValue(InBits); in WidenMaskArithmetic() local
16220 Mask = Mask.zext(VT.getScalarType().getSizeInBits()); in WidenMaskArithmetic()
16222 Op, DAG.getConstant(Mask, VT)); in WidenMaskArithmetic()
16325 SDValue Mask = N1.getOperand(0); in PerformOrCombine() local
16328 if (N0.getOperand(0) == Mask) in PerformOrCombine()
16330 if (N0.getOperand(1) == Mask) in PerformOrCombine()
16339 if (Mask.getOpcode() == ISD::BITCAST) in PerformOrCombine()
16340 Mask = Mask.getOperand(0); in PerformOrCombine()
16346 EVT MaskVT = Mask.getValueType(); in PerformOrCombine()
16351 if (Mask.getOpcode() != X86ISD::VSRAI) in PerformOrCombine()
16355 SDValue SraC = Mask.getOperand(1); in PerformOrCombine()
16371 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); in PerformOrCombine()
16372 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); in PerformOrCombine()
16382 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); in PerformOrCombine()
16383 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); in PerformOrCombine()
16384 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); in PerformOrCombine()
17007 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); in isHorizontalBinOp() local
17008 std::copy(Mask.begin(), Mask.end(), LMask.begin()); in isHorizontalBinOp()
17025 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); in isHorizontalBinOp() local
17026 std::copy(Mask.begin(), Mask.end(), RMask.begin()); in isHorizontalBinOp()