Lines Matching refs:SETCC
462 setOperationAction(ISD::SETCC , MVT::i8 , Custom); in X86TargetLowering()
463 setOperationAction(ISD::SETCC , MVT::i16 , Custom); in X86TargetLowering()
464 setOperationAction(ISD::SETCC , MVT::i32 , Custom); in X86TargetLowering()
465 setOperationAction(ISD::SETCC , MVT::f32 , Custom); in X86TargetLowering()
466 setOperationAction(ISD::SETCC , MVT::f64 , Custom); in X86TargetLowering()
467 setOperationAction(ISD::SETCC , MVT::f80 , Custom); in X86TargetLowering()
470 setOperationAction(ISD::SETCC , MVT::i64 , Custom); in X86TargetLowering()
801 setOperationAction(ISD::SETCC, VT, Expand); in X86TargetLowering()
911 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in X86TargetLowering()
912 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in X86TargetLowering()
913 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); in X86TargetLowering()
914 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); in X86TargetLowering()
1141 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); in X86TargetLowering()
1142 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in X86TargetLowering()
1143 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); in X86TargetLowering()
1144 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); in X86TargetLowering()
1343 setTargetDAGCombine(ISD::SETCC); in X86TargetLowering()
8942 UI->getOpcode() != ISD::SETCC && in EmitTest()
8982 User->getOpcode() != ISD::SETCC && in EmitTest()
9203 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerToBT()
9215 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC && in Lower256IntVSETCC()
9428 if (Op0.getOpcode() == X86ISD::SETCC) { in LowerSETCC()
9435 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC()
9447 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC()
9500 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
9510 if (Cond.getOpcode() == X86ISD::SETCC && in LowerSELECT()
9567 if (CondOpcode == X86ISD::SETCC || in LowerSELECT()
9736 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && in isAndOrOfSetCCs()
9738 Op.getOperand(1).getOpcode() == X86ISD::SETCC && in isAndOrOfSetCCs()
9749 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && in isXor1OfSetCC()
9764 if (Cond.getOpcode() == ISD::SETCC) { in LowerBRCOND()
9804 if (CondOpcode == X86ISD::SETCC || in LowerBRCOND()
9926 } else if (Cond.getOpcode() == ISD::SETCC && in LowerBRCOND()
9957 } else if (Cond.getOpcode() == ISD::SETCC && in LowerBRCOND()
10375 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN()
10672 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); in LowerINTRINSIC_WO_CHAIN()
10829 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN()
11765 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in LowerXALUO()
11778 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), in LowerXALUO()
12136 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
12430 case X86ISD::SETCC: return "X86ISD::SETCC"; in getTargetNodeName()
14686 case X86ISD::SETCC: in computeMaskedBitsForTargetNode()
15190 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && in PerformSELECTCombine()
15342 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. in PerformSELECTCombine()
15438 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && in PerformSELECTCombine()
15456 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && in PerformSELECTCombine()
15511 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) in PerformSELECTCombine()
15594 case X86ISD::SETCC: in checkBoolTestSetCCCombine()
15693 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in PerformCMOVCombine()
15710 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in PerformCMOVCombine()
15748 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in PerformCMOVCombine()
17389 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags); in PerformSETCCCombine()
17487 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) in OptimizeConditionalInDecrement()
17616 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); in PerformDAGCombine()
17617 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()