1079     addRegisterClass(MVT::v16i16, &X86::VR256RegClass);  in X86TargetLowering()
1130     setOperationAction(ISD::SRL,               MVT::v16i16, Custom);  in X86TargetLowering()
1133     setOperationAction(ISD::SHL,               MVT::v16i16, Custom);  in X86TargetLowering()
1136     setOperationAction(ISD::SRA,               MVT::v16i16, Custom);  in X86TargetLowering()
1139     setOperationAction(ISD::SDIV,              MVT::v16i16, Custom);  in X86TargetLowering()
1142     setOperationAction(ISD::SETCC,             MVT::v16i16, Custom);  in X86TargetLowering()
1174       setOperationAction(ISD::ADD,             MVT::v16i16, Legal);  in X86TargetLowering()
1179       setOperationAction(ISD::SUB,             MVT::v16i16, Legal);  in X86TargetLowering()
1184       setOperationAction(ISD::MUL,             MVT::v16i16, Legal);  in X86TargetLowering()
1201       setOperationAction(ISD::ADD,             MVT::v16i16, Custom);  in X86TargetLowering()
1206       setOperationAction(ISD::SUB,             MVT::v16i16, Custom);  in X86TargetLowering()
1211       setOperationAction(ISD::MUL,             MVT::v16i16, Custom);  in X86TargetLowering()
3344   if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))  in isPSHUFHWMask()
3356   if (VT == MVT::v16i16) {  in isPSHUFHWMask()
3373   if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))  in isPSHUFLWMask()
3385   if (VT == MVT::v16i16) {  in isPSHUFLWMask()
4114   assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&  in getShufflePSHUFHWImmediate()
4138   assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&  in getShufflePSHUFLWImmediate()
5708   if (!Subtarget->hasInt256() && VT == MVT::v16i16)  in LowerVECTOR_SHUFFLEtoBlend()
6202   case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;  in RewriteAsNarrowerShuffle()
6750       VT == MVT::v16i16 || VT == MVT::v32i8) {  in NormalizeVectorShuffle()
11512            (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {  in LowerShift()
11571           SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,  in LowerShift()
11583           SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,  in LowerShift()
11801     case MVT::v16i16:  in LowerSIGN_EXTEND_INREG()
15114   case MVT::v16i16:  in matchIntegerMINMAX()
15459        (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {  in PerformSELECTCombine()
15938        (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))  in PerformShiftCombine()
16017     case MVT::v16i16:  in PerformShiftCombine()
16026     case MVT::v16i16:  in PerformShiftCombine()
16037     case MVT::v16i16:  in PerformShiftCombine()
17523        (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&  in PerformAddCombine()
17556        (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&  in PerformSubCombine()
18236       case MVT::v16i16:  in getRegForInlineAsmConstraint()