Lines Matching refs:def
24 def sub_8bit : SubRegIndex;
25 def sub_8bit_hi : SubRegIndex;
26 def sub_16bit : SubRegIndex;
27 def sub_32bit : SubRegIndex;
28 def sub_xmm : SubRegIndex;
47 def AL : X86Reg<"al", 0>;
48 def DL : X86Reg<"dl", 2>;
49 def CL : X86Reg<"cl", 1>;
50 def BL : X86Reg<"bl", 3>;
54 def AH : X86Reg<"ah", 4>;
55 def DH : X86Reg<"dh", 6>;
56 def CH : X86Reg<"ch", 5>;
57 def BH : X86Reg<"bh", 7>;
61 def SIL : X86Reg<"sil", 6>;
62 def DIL : X86Reg<"dil", 7>;
63 def BPL : X86Reg<"bpl", 5>;
64 def SPL : X86Reg<"spl", 4>;
65 def R8B : X86Reg<"r8b", 8>;
66 def R9B : X86Reg<"r9b", 9>;
67 def R10B : X86Reg<"r10b", 10>;
68 def R11B : X86Reg<"r11b", 11>;
69 def R12B : X86Reg<"r12b", 12>;
70 def R13B : X86Reg<"r13b", 13>;
71 def R14B : X86Reg<"r14b", 14>;
72 def R15B : X86Reg<"r15b", 15>;
77 def AX : X86Reg<"ax", 0, [AL,AH]>;
78 def DX : X86Reg<"dx", 2, [DL,DH]>;
79 def CX : X86Reg<"cx", 1, [CL,CH]>;
80 def BX : X86Reg<"bx", 3, [BL,BH]>;
83 def SI : X86Reg<"si", 6, [SIL]>;
84 def DI : X86Reg<"di", 7, [DIL]>;
85 def BP : X86Reg<"bp", 5, [BPL]>;
86 def SP : X86Reg<"sp", 4, [SPL]>;
88 def IP : X86Reg<"ip", 0>;
92 def R8W : X86Reg<"r8w", 8, [R8B]>;
93 def R9W : X86Reg<"r9w", 9, [R9B]>;
94 def R10W : X86Reg<"r10w", 10, [R10B]>;
95 def R11W : X86Reg<"r11w", 11, [R11B]>;
96 def R12W : X86Reg<"r12w", 12, [R12B]>;
97 def R13W : X86Reg<"r13w", 13, [R13B]>;
98 def R14W : X86Reg<"r14w", 14, [R14B]>;
99 def R15W : X86Reg<"r15w", 15, [R15B]>;
104 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
105 def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
106 def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
107 def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
108 def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
109 def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
110 def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
111 def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
112 def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
116 def R8D : X86Reg<"r8d", 8, [R8W]>;
117 def R9D : X86Reg<"r9d", 9, [R9W]>;
118 def R10D : X86Reg<"r10d", 10, [R10W]>;
119 def R11D : X86Reg<"r11d", 11, [R11W]>;
120 def R12D : X86Reg<"r12d", 12, [R12W]>;
121 def R13D : X86Reg<"r13d", 13, [R13W]>;
122 def R14D : X86Reg<"r14d", 14, [R14W]>;
123 def R15D : X86Reg<"r15d", 15, [R15W]>;
128 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
129 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
130 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
131 def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
132 def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
133 def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
134 def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
135 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
139 def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
140 def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
141 def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
142 def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
143 def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
144 def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
145 def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
146 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
147 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
151 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
152 def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
153 def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
154 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
155 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
156 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
157 def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
158 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
161 def FP0 : X86Reg<"fp0", 0>;
162 def FP1 : X86Reg<"fp1", 0>;
163 def FP2 : X86Reg<"fp2", 0>;
164 def FP3 : X86Reg<"fp3", 0>;
165 def FP4 : X86Reg<"fp4", 0>;
166 def FP5 : X86Reg<"fp5", 0>;
167 def FP6 : X86Reg<"fp6", 0>;
170 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
171 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
172 def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
173 def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
174 def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
175 def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
176 def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
177 def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
181 def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
182 def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
183 def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
184 def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
185 def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
186 def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
187 def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
188 def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
193 def YMM0: X86Reg<"ymm0", 0, [XMM0]>, DwarfRegAlias<XMM0>;
194 def YMM1: X86Reg<"ymm1", 1, [XMM1]>, DwarfRegAlias<XMM1>;
195 def YMM2: X86Reg<"ymm2", 2, [XMM2]>, DwarfRegAlias<XMM2>;
196 def YMM3: X86Reg<"ymm3", 3, [XMM3]>, DwarfRegAlias<XMM3>;
197 def YMM4: X86Reg<"ymm4", 4, [XMM4]>, DwarfRegAlias<XMM4>;
198 def YMM5: X86Reg<"ymm5", 5, [XMM5]>, DwarfRegAlias<XMM5>;
199 def YMM6: X86Reg<"ymm6", 6, [XMM6]>, DwarfRegAlias<XMM6>;
200 def YMM7: X86Reg<"ymm7", 7, [XMM7]>, DwarfRegAlias<XMM7>;
201 def YMM8: X86Reg<"ymm8", 8, [XMM8]>, DwarfRegAlias<XMM8>;
202 def YMM9: X86Reg<"ymm9", 9, [XMM9]>, DwarfRegAlias<XMM9>;
203 def YMM10: X86Reg<"ymm10", 10, [XMM10]>, DwarfRegAlias<XMM10>;
204 def YMM11: X86Reg<"ymm11", 11, [XMM11]>, DwarfRegAlias<XMM11>;
205 def YMM12: X86Reg<"ymm12", 12, [XMM12]>, DwarfRegAlias<XMM12>;
206 def YMM13: X86Reg<"ymm13", 13, [XMM13]>, DwarfRegAlias<XMM13>;
207 def YMM14: X86Reg<"ymm14", 14, [XMM14]>, DwarfRegAlias<XMM14>;
208 def YMM15: X86Reg<"ymm15", 15, [XMM15]>, DwarfRegAlias<XMM15>;
219 def ST0 : STRegister<"st(0)", 0, []>, DwarfRegNum<[33, 12, 11]>;
220 def ST1 : STRegister<"st(1)", 1, [FP6]>, DwarfRegNum<[34, 13, 12]>;
221 def ST2 : STRegister<"st(2)", 2, [FP5]>, DwarfRegNum<[35, 14, 13]>;
222 def ST3 : STRegister<"st(3)", 3, [FP4]>, DwarfRegNum<[36, 15, 14]>;
223 def ST4 : STRegister<"st(4)", 4, [FP3]>, DwarfRegNum<[37, 16, 15]>;
224 def ST5 : STRegister<"st(5)", 5, [FP2]>, DwarfRegNum<[38, 17, 16]>;
225 def ST6 : STRegister<"st(6)", 6, [FP1]>, DwarfRegNum<[39, 18, 17]>;
226 def ST7 : STRegister<"st(7)", 7, [FP0]>, DwarfRegNum<[40, 19, 18]>;
229 def FPSW : X86Reg<"fpsw", 0>;
232 def EFLAGS : X86Reg<"flags", 0>;
235 def CS : X86Reg<"cs", 1>;
236 def DS : X86Reg<"ds", 3>;
237 def SS : X86Reg<"ss", 2>;
238 def ES : X86Reg<"es", 0>;
239 def FS : X86Reg<"fs", 4>;
240 def GS : X86Reg<"gs", 5>;
243 def DR0 : X86Reg<"dr0", 0>;
244 def DR1 : X86Reg<"dr1", 1>;
245 def DR2 : X86Reg<"dr2", 2>;
246 def DR3 : X86Reg<"dr3", 3>;
247 def DR4 : X86Reg<"dr4", 4>;
248 def DR5 : X86Reg<"dr5", 5>;
249 def DR6 : X86Reg<"dr6", 6>;
250 def DR7 : X86Reg<"dr7", 7>;
253 def CR0 : X86Reg<"cr0", 0>;
254 def CR1 : X86Reg<"cr1", 1>;
255 def CR2 : X86Reg<"cr2", 2>;
256 def CR3 : X86Reg<"cr3", 3>;
257 def CR4 : X86Reg<"cr4", 4>;
258 def CR5 : X86Reg<"cr5", 5>;
259 def CR6 : X86Reg<"cr6", 6>;
260 def CR7 : X86Reg<"cr7", 7>;
261 def CR8 : X86Reg<"cr8", 8>;
262 def CR9 : X86Reg<"cr9", 9>;
263 def CR10 : X86Reg<"cr10", 10>;
264 def CR11 : X86Reg<"cr11", 11>;
265 def CR12 : X86Reg<"cr12", 12>;
266 def CR13 : X86Reg<"cr13", 13>;
267 def CR14 : X86Reg<"cr14", 14>;
268 def CR15 : X86Reg<"cr15", 15>;
271 def EIZ : X86Reg<"eiz", 4>;
272 def RIZ : X86Reg<"riz", 4>;
292 def GR8 : RegisterClass<"X86", [i8], 8,
301 def GR16 : RegisterClass<"X86", [i16], 16,
305 def GR32 : RegisterClass<"X86", [i32], 32,
312 def GR64 : RegisterClass<"X86", [i64], 64,
319 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
322 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
325 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
333 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
334 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
335 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
336 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
337 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
338 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>;
339 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
341 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
345 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
353 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
356 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
359 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
365 def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)>;
368 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
371 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
375 def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
379 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
383 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
386 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
388 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
397 def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;
398 def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
399 def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
404 def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
409 def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
410 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
412 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
416 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
420 def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {