896   for (unsigned rci = RegClasses.size(); rci; --rci) {  in computeSubClasses()  local
897     CodeGenRegisterClass &RC = *RegClasses[rci - 1];  in computeSubClasses()
902     for (unsigned s = rci; s != RegClasses.size(); ++s) {  in computeSubClasses()
914     for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)  in computeSubClasses()
919   for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {  in computeSubClasses()  local
920     const BitVector &SC = RegClasses[rci]->getSubClasses();  in computeSubClasses()
922       if (unsigned(s) == rci)  in computeSubClasses()
924       RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);  in computeSubClasses()
931   for (unsigned rci = 0; rci != RegClasses.size(); ++rci)  in computeSubClasses()  local
932     if (!RegClasses[rci]->getDef())  in computeSubClasses()
933       RegClasses[rci]->inheritProperties(RegBank);  in computeSubClasses()
1653   for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {  in inferCommonSubClass()  local
1655     CodeGenRegisterClass *RC2 = RegClasses[rci];  in inferCommonSubClass()
1762     for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce;  in inferMatchingSuperRegClass()  local
1763          ++rci) {  in inferMatchingSuperRegClass()
1764       CodeGenRegisterClass *SubRC = RegClasses[rci];  in inferMatchingSuperRegClass()
1800   for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {  in computeInferredRegisterClasses()  local
1801     CodeGenRegisterClass *RC = RegClasses[rci];  in computeInferredRegisterClasses()
1818     if (rci + 1 == FirstNewRC) {  in computeInferredRegisterClasses()