140   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");  in collectProcModels()
183 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,  in scanSchedRW()
190     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");  in scanSchedRW()
196     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");  in scanSchedRW()
199       RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");  in scanSchedRW()
216   RecVec SWDefs, SRDefs;  in collectSchedRW()
222     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");  in collectSchedRW()
233   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedRW()
236     RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
248   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectSchedRW()
251     RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
264   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");  in collectSchedRW()
322     RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");  in collectSchedRW()
363     RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");  in hasReadOfWrite()
373 void splitSchedReadWrites(const RecVec &RWDefs,  in splitSchedReadWrites()
374                           RecVec &WriteDefs, RecVec &ReadDefs) {  in splitSchedReadWrites()
387 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,  in findRWs()
389     RecVec WriteDefs;  in findRWs()
390     RecVec ReadDefs;  in findRWs()
397 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,  in findRWs()
526   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedClasses()
567     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in collectSchedClasses()
632 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {  in createSchedClassName()
685   const RecVec *InstDefs = Sets.expand(InstRWDef);  in createInstRWClass()
771     RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");  in collectProcItins()
810   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectProcItinRW()
856       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in inferFromItinClass()
874   const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in inferFromInstRWs()
876     const RecVec *InstDefs = Sets.expand(*RWI);  in inferFromInstRWs()
972     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in mutuallyExclusive()
1048     const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1066       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1129     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");  in pushVariant()
1292     RecVec Preds;  in inferFromTransitions()
1391   RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");  in collectProcResources()
1396   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");  in collectProcResources()
1445       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in collectItinProcResources()
1519   RecVec ProcResourceDefs =  in findProcResUnits()
1535   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");  in findProcResUnits()
1584   RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;  in addWriteRes()
1591   RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");  in addWriteRes()
1601   RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;  in addReadAdvance()