Lines Matching refs:RC
172 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; in EmitRegUnitPressure() local
173 const CodeGenRegister::Set &Regs = RC.getMembers(); in EmitRegUnitPressure()
178 RC.buildRegUnitSet(RegUnits); in EmitRegUnitPressure()
182 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
846 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
847 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
850 std::string Name = RC.getName(); in runMCDesc()
880 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
884 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); in runMCDesc()
885 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); in runMCDesc()
886 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); in runMCDesc()
888 OS << " { " << '\"' << RC.getName() << "\", " in runMCDesc()
889 << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
890 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc()
891 << RC.getQualifiedName() + "RegClassID" << ", " in runMCDesc()
892 << RC.SpillSize/8 << ", " in runMCDesc()
893 << RC.SpillAlignment/8 << ", " in runMCDesc()
894 << RC.CopyCost << ", " in runMCDesc()
895 << RC.Allocatable << " },\n"; in runMCDesc()
988 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetHeader() local
989 const std::string &Name = RC.getName(); in runTargetHeader()
1026 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1027 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1029 if (RC.Allocatable) in runTargetDesc()
1091 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1092 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; in runTargetDesc()
1093 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1101 RC.getSuperRegClasses(Idx, MaskBV); in runTargetDesc()
1120 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1121 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); in runTargetDesc()
1128 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1136 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
1137 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1138 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1140 << RC.AltOrderSelect << "}\n\n" in runTargetDesc()
1141 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1143 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { in runTargetDesc()
1144 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1153 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" in runTargetDesc()
1156 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) in runTargetDesc()
1157 if (RC.getOrder(oi).empty()) in runTargetDesc()
1161 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1162 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() in runTargetDesc()
1172 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
1175 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() in runTargetDesc()
1177 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " in runTargetDesc()
1178 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1180 if (RC.getSuperClasses().empty()) in runTargetDesc()
1183 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1184 if (RC.AltOrderSelect.empty()) in runTargetDesc()
1187 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1238 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; in runTargetDesc() local
1239 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1242 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) in runTargetDesc()