Lines Matching refs:rn
1187 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) in gen_op_iwmmxt_movq_wRn_M0() argument
1189 iwmmxt_store_reg(cpu_M0, rn); in gen_op_iwmmxt_movq_wRn_M0()
1192 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) in gen_op_iwmmxt_movq_M0_wRn() argument
1194 iwmmxt_load_reg(cpu_M0, rn); in gen_op_iwmmxt_movq_M0_wRn()
1197 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) in gen_op_iwmmxt_orq_M0_wRn() argument
1199 iwmmxt_load_reg(cpu_V1, rn); in gen_op_iwmmxt_orq_M0_wRn()
1203 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) in gen_op_iwmmxt_andq_M0_wRn() argument
1205 iwmmxt_load_reg(cpu_V1, rn); in gen_op_iwmmxt_andq_M0_wRn()
1209 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) in gen_op_iwmmxt_xorq_M0_wRn() argument
1211 iwmmxt_load_reg(cpu_V1, rn); in gen_op_iwmmxt_xorq_M0_wRn()
1216 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1218 iwmmxt_load_reg(cpu_V1, rn); \
1313 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) in gen_op_iwmmxt_addl_M0_wRn() argument
1315 iwmmxt_load_reg(cpu_V1, rn); in gen_op_iwmmxt_addl_M0_wRn()
2727 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; in disas_vfp_insn() local
2740 rn = (insn >> 16) & 0xf; in disas_vfp_insn()
2741 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC in disas_vfp_insn()
2742 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) in disas_vfp_insn()
2755 VFP_DREG_N(rn, insn); in disas_vfp_insn()
2775 tmp = neon_load_reg(rn, pass); in disas_vfp_insn()
2817 neon_store_reg(rn, n, tmp2); in disas_vfp_insn()
2819 neon_store_reg(rn, n, tmp); in disas_vfp_insn()
2824 tmp2 = neon_load_reg(rn, pass); in disas_vfp_insn()
2829 tmp2 = neon_load_reg(rn, pass); in disas_vfp_insn()
2836 neon_store_reg(rn, pass, tmp); in disas_vfp_insn()
2842 rn = VFP_SREG_N(insn); in disas_vfp_insn()
2847 rn >>= 1; in disas_vfp_insn()
2849 switch (rn) { in disas_vfp_insn()
2857 tmp = load_cpu_field(vfp.xregs[rn]); in disas_vfp_insn()
2862 tmp = load_cpu_field(vfp.xregs[rn]); in disas_vfp_insn()
2870 tmp = load_cpu_field(vfp.xregs[rn]); in disas_vfp_insn()
2886 tmp = load_cpu_field(vfp.xregs[rn]); in disas_vfp_insn()
2892 gen_mov_F0_vreg(0, rn); in disas_vfp_insn()
2906 rn >>= 1; in disas_vfp_insn()
2908 switch (rn) { in disas_vfp_insn()
2925 store_cpu_field(tmp, vfp.xregs[rn]); in disas_vfp_insn()
2930 store_cpu_field(tmp, vfp.xregs[rn]); in disas_vfp_insn()
2937 gen_mov_vreg_F0(0, rn); in disas_vfp_insn()
2948 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1); in disas_vfp_insn()
2951 VFP_DREG_N(rn, insn); in disas_vfp_insn()
2954 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) { in disas_vfp_insn()
2961 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) { in disas_vfp_insn()
2970 rn = VFP_SREG_N(insn); in disas_vfp_insn()
2971 if (op == 15 && rn == 15) { in disas_vfp_insn()
2984 if (op == 15 && rn > 3) in disas_vfp_insn()
3020 switch (rn) { in disas_vfp_insn()
3056 gen_mov_F0_vreg(dp, rn); in disas_vfp_insn()
3131 switch (rn) { in disas_vfp_insn()
3263 printf ("rn:%d\n", rn); in disas_vfp_insn()
3273 if (op == 15 && (rn >= 8 && rn <= 11)) in disas_vfp_insn()
3275 else if (op == 15 && dp && ((rn & 0x1c) == 0x18)) in disas_vfp_insn()
3278 else if (op == 15 && rn == 15) in disas_vfp_insn()
3309 rn = ((rn + delta_d) & (bank_mask - 1)) in disas_vfp_insn()
3310 | (rn & bank_mask); in disas_vfp_insn()
3311 gen_mov_F0_vreg(dp, rn); in disas_vfp_insn()
3325 rn = (insn >> 16) & 0xf; in disas_vfp_insn()
3341 store_reg(s, rn, tmp); in disas_vfp_insn()
3348 store_reg(s, rn, tmp); in disas_vfp_insn()
3356 tmp = load_reg(s, rn); in disas_vfp_insn()
3363 tmp = load_reg(s, rn); in disas_vfp_insn()
3370 rn = (insn >> 16) & 0xf; in disas_vfp_insn()
3375 if (s->thumb && rn == 15) { in disas_vfp_insn()
3379 addr = load_reg(s, rn); in disas_vfp_insn()
3434 store_reg(s, rn, addr); in disas_vfp_insn()
3829 int rd, rn, rm; in disas_neon_ls_insn() local
3847 rn = (insn >> 16) & 0xf; in disas_neon_ls_insn()
3906 load_reg_var(s, addr, rn); in disas_neon_ls_insn()
3986 load_reg_var(s, addr, rn); in disas_neon_ls_insn()
4034 base = load_reg(s, rn); in disas_neon_ls_insn()
4043 store_reg(s, rn, base); in disas_neon_ls_insn()
4420 int rd, rn, rm; in disas_neon_data_insn() local
4436 VFP_DREG_N(rn, insn); in disas_neon_data_insn()
4449 if (q && ((rd | rn | rm) & 1)) { in disas_neon_data_insn()
4455 neon_load_reg64(cpu_V0, rn + pass); in disas_neon_data_insn()
4523 rtmp = rn; in disas_neon_data_insn()
4524 rn = rm; in disas_neon_data_insn()
4579 tmp = neon_load_reg(rn, 0); in disas_neon_data_insn()
4580 tmp2 = neon_load_reg(rn, 1); in disas_neon_data_insn()
4587 tmp = neon_load_reg(rn, pass); in disas_neon_data_insn()
5308 if ((src1_wide && (rn & 1)) || in disas_neon_data_insn()
5320 } else if (rd == rn && !src1_wide) { in disas_neon_data_insn()
5321 tmp = neon_load_reg(rn, 1); in disas_neon_data_insn()
5327 neon_load_reg64(cpu_V0, rn + pass); in disas_neon_data_insn()
5330 if (pass == 1 && rd == rn) { in disas_neon_data_insn()
5333 tmp = neon_load_reg(rn, pass); in disas_neon_data_insn()
5486 if (u && ((rd | rn) & 1)) { in disas_neon_data_insn()
5493 tmp2 = neon_load_reg(rn, pass); in disas_neon_data_insn()
5559 tmp3 = neon_load_reg(rn, 1); in disas_neon_data_insn()
5563 tmp = neon_load_reg(rn, 0); in disas_neon_data_insn()
5612 if (q && ((rd | rn | rm) & 1)) { in disas_neon_data_insn()
5617 neon_load_reg64(cpu_V0, rn); in disas_neon_data_insn()
5619 neon_load_reg64(cpu_V1, rn + 1); in disas_neon_data_insn()
5622 neon_load_reg64(cpu_V0, rn + 1); in disas_neon_data_insn()
5629 neon_load_reg64(cpu_V0, rn); in disas_neon_data_insn()
5630 neon_load_reg64(tmp64, rn + 1); in disas_neon_data_insn()
5632 neon_load_reg64(cpu_V0, rn + 1); in disas_neon_data_insn()
5650 neon_load_reg64(cpu_V0, rn); in disas_neon_data_insn()
6015 if ((rn + n) > 32) { in disas_neon_data_insn()
6029 tmp4 = tcg_const_i32(rn); in disas_neon_data_insn()
6417 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; in disas_arm_insn() local
6563 rn = (insn >> 16) & 0xf; in disas_arm_insn()
6564 addr = load_reg(s, rn); in disas_arm_insn()
6590 store_reg(s, rn, addr); in disas_arm_insn()
6767 rn = (insn >> 16) & 0xf; in disas_arm_insn()
6769 tmp2 = load_reg(s, rn); in disas_arm_insn()
6800 rn = (insn >> 12) & 0xf; in disas_arm_insn()
6816 tmp2 = load_reg(s, rn); in disas_arm_insn()
6831 gen_addq(s, tmp64, rn, rd); in disas_arm_insn()
6832 gen_storeq_reg(s, rn, rd, tmp64); in disas_arm_insn()
6836 tmp2 = load_reg(s, rn); in disas_arm_insn()
6884 rn = (insn >> 16) & 0xf; in disas_arm_insn()
6885 tmp = load_reg(s, rn); in disas_arm_insn()
7039 rn = (insn >> 12) & 0xf; in disas_arm_insn()
7053 tmp2 = load_reg(s, rn); in disas_arm_insn()
7058 tmp2 = load_reg(s, rn); in disas_arm_insn()
7072 gen_addq_lo(s, tmp64, rn); in disas_arm_insn()
7074 gen_storeq_reg(s, rn, rd, tmp64); in disas_arm_insn()
7088 gen_addq(s, tmp64, rn, rd); in disas_arm_insn()
7093 gen_storeq_reg(s, rn, rd, tmp64); in disas_arm_insn()
7100 rn = (insn >> 16) & 0xf; in disas_arm_insn()
7110 load_reg_var(s, addr, rn); in disas_arm_insn()
7155 addr = load_reg(s, rn); in disas_arm_insn()
7172 rn = (insn >> 16) & 0xf; in disas_arm_insn()
7174 addr = load_reg(s, rn); in disas_arm_insn()
7226 store_reg(s, rn, addr); in disas_arm_insn()
7230 store_reg(s, rn, addr); in disas_arm_insn()
7249 rn = (insn >> 16) & 0xf; in disas_arm_insn()
7255 tmp = load_reg(s, rn); in disas_arm_insn()
7267 tmp = load_reg(s, rn); in disas_arm_insn()
7319 tmp = load_reg(s, rn); in disas_arm_insn()
7344 if (rn != 15) { in disas_arm_insn()
7345 tmp2 = load_reg(s, rn); in disas_arm_insn()
7398 store_reg(s, rn, tmp); in disas_arm_insn()
7419 gen_addq(s, tmp64, rd, rn); in disas_arm_insn()
7420 gen_storeq_reg(s, rd, rn, tmp64); in disas_arm_insn()
7430 store_reg(s, rn, tmp); in disas_arm_insn()
7448 store_reg(s, rn, tmp); in disas_arm_insn()
7504 rn = (insn >> 16) & 0xf; in disas_arm_insn()
7506 tmp2 = load_reg(s, rn); in disas_arm_insn()
7527 store_reg(s, rn, tmp2); in disas_arm_insn()
7529 store_reg(s, rn, tmp2); in disas_arm_insn()
7553 rn = (insn >> 16) & 0xf; in disas_arm_insn()
7554 addr = load_reg(s, rn); in disas_arm_insn()
7594 } else if (i == rn) { in disas_arm_insn()
7642 store_reg(s, rn, addr); in disas_arm_insn()
7648 store_reg(s, rn, loaded_var); in disas_arm_insn()
7782 uint32_t rd, rn, rm, rs; in disas_thumb2_insn() local
7844 rn = (insn >> 16) & 0xf; in disas_thumb2_insn()
7857 if (rn == 15) { in disas_thumb2_insn()
7861 addr = load_reg(s, rn); in disas_thumb2_insn()
7887 if (rn == 15) in disas_thumb2_insn()
7890 store_reg(s, rn, addr); in disas_thumb2_insn()
7897 load_reg_var(s, addr, rn); in disas_thumb2_insn()
7907 if (rn == 15) { in disas_thumb2_insn()
7911 addr = load_reg(s, rn); in disas_thumb2_insn()
7936 load_reg_var(s, addr, rn); in disas_thumb2_insn()
7952 addr = load_reg(s, rn); in disas_thumb2_insn()
7966 store_reg(s, rn, addr); in disas_thumb2_insn()
8004 addr = load_reg(s, rn); in disas_thumb2_insn()
8024 } else if (i == rn) { in disas_thumb2_insn()
8038 store_reg(s, rn, loaded_var); in disas_thumb2_insn()
8047 if (insn & (1 << rn)) in disas_thumb2_insn()
8049 store_reg(s, rn, addr); in disas_thumb2_insn()
8061 tmp = load_reg(s, rn); in disas_thumb2_insn()
8083 if (rn == 15) { in disas_thumb2_insn()
8087 tmp = load_reg(s, rn); in disas_thumb2_insn()
8112 tmp = load_reg(s, rn); in disas_thumb2_insn()
8140 if (rn != 15) { in disas_thumb2_insn()
8141 tmp2 = load_reg(s, rn); in disas_thumb2_insn()
8156 tmp = load_reg(s, rn); in disas_thumb2_insn()
8166 tmp = load_reg(s, rn); in disas_thumb2_insn()
8176 tmp = load_reg(s, rn); in disas_thumb2_insn()
8209 tmp = load_reg(s, rn); in disas_thumb2_insn()
8305 tmp = load_reg(s, rn); in disas_thumb2_insn()
8426 tmp = load_reg(s, rn); in disas_thumb2_insn()
8438 tmp = load_reg(s, rn); in disas_thumb2_insn()
8489 tmp = load_reg(s, rn); in disas_thumb2_insn()
8496 if (rn != 14 || rd != 15) { in disas_thumb2_insn()
8499 tmp = load_reg(s, rn); in disas_thumb2_insn()
8555 if (rn == 15) { in disas_thumb2_insn()
8559 tmp = load_reg(s, rn); in disas_thumb2_insn()
8631 if (rn == 15) { in disas_thumb2_insn()
8640 tmp = load_reg(s, rn); in disas_thumb2_insn()
8678 rn = (insn >> 16) & 0xf; in disas_thumb2_insn()
8679 if (rn == 15) { in disas_thumb2_insn()
8683 tmp = load_reg(s, rn); in disas_thumb2_insn()
8731 if (rn == 15) { in disas_thumb2_insn()
8746 if (rn == 15) { in disas_thumb2_insn()
8757 addr = load_reg(s, rn); in disas_thumb2_insn()
8836 store_reg(s, rn, addr); in disas_thumb2_insn()
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond; in disas_thumb_insn() local
8883 rn = (insn >> 3) & 7; in disas_thumb_insn()
8884 tmp = load_reg(s, rn); in disas_thumb_insn()
9150 rn = (insn >> 3) & 7; in disas_thumb_insn()
9153 addr = load_reg(s, rn); in disas_thumb_insn()
9195 rn = (insn >> 3) & 7; in disas_thumb_insn()
9196 addr = load_reg(s, rn); in disas_thumb_insn()
9215 rn = (insn >> 3) & 7; in disas_thumb_insn()
9216 addr = load_reg(s, rn); in disas_thumb_insn()
9235 rn = (insn >> 3) & 7; in disas_thumb_insn()
9236 addr = load_reg(s, rn); in disas_thumb_insn()
9404 rn = (insn >> 3) & 0x7; in disas_thumb_insn()
9406 tmp = load_reg(s, rn); in disas_thumb_insn()
9455 rn = (insn >> 8) & 0x7; in disas_thumb_insn()
9456 addr = load_reg(s, rn); in disas_thumb_insn()
9462 if (i == rn) { in disas_thumb_insn()
9476 if ((insn & (1 << rn)) == 0) { in disas_thumb_insn()
9478 store_reg(s, rn, addr); in disas_thumb_insn()
9482 store_reg(s, rn, loaded_var); in disas_thumb_insn()