Lines Matching refs:vassert
177 do { vassert(__curr_is_Thumb); } while (0)
180 do { vassert(! __curr_is_Thumb); } while (0)
211 vassert(sh >= 0 && sh < 32); in ROR32()
286 vassert(i < 256); in mkU8()
334 vassert(isPlausibleIRType(ty)); in newTemp()
348 vassert(rot >= 0 && rot < 32); in genROR32()
467 default: vassert(0); in integerGuestRegOffset()
474 vassert(iregNo < 16); in llGetIReg()
484 vassert(iregNo < 16); in getIRegA()
492 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in getIRegA()
506 vassert(iregNo < 16); in getIRegT()
509 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in getIRegT()
521 vassert(iregNo < 16); in llPutIReg()
522 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); in llPutIReg()
558 vassert(r15written == False); in putIRegA()
559 vassert(r15guard == IRTemp_INVALID); in putIRegA()
560 vassert(r15kind == Ijk_Boring); in putIRegA()
578 vassert(iregNo >= 0 && iregNo <= 14); in putIRegT()
596 vassert(r <= 15); in isBadRegT()
642 default: vassert(0); in doubleGuestRegOffset()
649 vassert(dregNo < 32); in llGetDReg()
661 vassert(dregNo < 32); in llPutDReg()
662 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); in llPutDReg()
693 vassert(dregNo < 32); in llGetDRegI64()
705 vassert(dregNo < 32); in llPutDRegI64()
706 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); in llPutDRegI64()
753 default: vassert(0); in quadGuestRegOffset()
760 vassert(qregNo < 16); in llGetQReg()
772 vassert(qregNo < 16); in llPutQReg()
773 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); in llPutQReg()
806 vassert(fregNo < 32); in floatGuestRegOffset()
809 vassert(0); in floatGuestRegOffset()
820 vassert(fregNo < 32); in llGetFReg()
832 vassert(fregNo < 32); in llPutFReg()
833 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32); in llPutFReg()
871 default: vassert(0); /* awaiting more cases */ in putMiscReg32()
873 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); in putMiscReg32()
942 vassert( flagNo >= 0 && flagNo <= 3 ); in put_GEFLAG32()
943 vassert( lowbits_to_ignore == 0 || in put_GEFLAG32()
955 default: vassert(0); in put_GEFLAG32()
968 default: vassert(0); in get_GEFLAG32()
1090 vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I32); in mk_armg_calculate_condition_dyn()
1134 vassert(cond >= 0 && cond <= 15); in mk_armg_calculate_condition()
1310 vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32)); in setFlags_D1_D2_ND()
1311 vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32)); in setFlags_D1_D2_ND()
1312 vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32)); in setFlags_D1_D2_ND()
1313 vassert(cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBER); in setFlags_D1_D2_ND()
1396 vassert(guardT != IRTemp_INVALID); in mk_skip_over_A32_if_cond_is_false()
1397 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in mk_skip_over_A32_if_cond_is_false()
1413 vassert(guardT != IRTemp_INVALID); in mk_skip_over_T16_if_cond_is_false()
1414 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in mk_skip_over_T16_if_cond_is_false()
1431 vassert(guardT != IRTemp_INVALID); in mk_skip_over_T32_if_cond_is_false()
1432 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in mk_skip_over_T32_if_cond_is_false()
1448 vassert(t != IRTemp_INVALID); in gen_SIGILL_T_if_nonzero()
1449 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in gen_SIGILL_T_if_nonzero()
1545 vassert(write_nzcvq || write_ge); in desynthesise_APSR()
1744 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_LSL_by_imm5()
1858 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_LSR_by_imm5()
1970 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_ASR_by_imm5()
2150 vassert(shift_amt < 32); in compute_result_and_C_after_shift_by_imm5()
2151 vassert(how < 4); in compute_result_and_C_after_shift_by_imm5()
2194 vassert(shift_amt >= 1 && shift_amt <= 31); in compute_result_and_C_after_shift_by_imm5()
2213 vassert(0); in compute_result_and_C_after_shift_by_imm5()
2244 vassert(how < 4); in compute_result_and_C_after_shift_by_reg()
2272 vassert(0); in compute_result_and_C_after_shift_by_reg()
2297 vassert(insn_25 <= 0x1); in mk_shifter_operand()
2298 vassert(insn_11_0 <= 0xFFF); in mk_shifter_operand()
2300 vassert(shop && *shop == IRTemp_INVALID); in mk_shifter_operand()
2304 vassert(*shco == IRTemp_INVALID); in mk_shifter_operand()
2314 vassert(rot <= 30); in mk_shifter_operand()
2339 vassert(shift_amt <= 31); in mk_shifter_operand()
2379 vassert(rN < 16); in mk_EA_reg_plusminus_imm12()
2380 vassert(bU < 2); in mk_EA_reg_plusminus_imm12()
2381 vassert(imm12 < 0x1000); in mk_EA_reg_plusminus_imm12()
2399 vassert(rN < 16); in mk_EA_reg_plusminus_shifted_reg()
2400 vassert(bU < 2); in mk_EA_reg_plusminus_shifted_reg()
2401 vassert(rM < 16); in mk_EA_reg_plusminus_shifted_reg()
2402 vassert(sh2 < 4); in mk_EA_reg_plusminus_shifted_reg()
2403 vassert(imm5 < 32); in mk_EA_reg_plusminus_shifted_reg()
2415 vassert(0); // ATC in mk_EA_reg_plusminus_shifted_reg()
2427 vassert(0); // ATC in mk_EA_reg_plusminus_shifted_reg()
2447 vassert(imm5 >= 1 && imm5 <= 31); in mk_EA_reg_plusminus_shifted_reg()
2455 vassert(0); in mk_EA_reg_plusminus_shifted_reg()
2457 vassert(index); in mk_EA_reg_plusminus_shifted_reg()
2468 vassert(rN < 16); in mk_EA_reg_plusminus_imm8()
2469 vassert(bU < 2); in mk_EA_reg_plusminus_imm8()
2470 vassert(imm8 < 0x100); in mk_EA_reg_plusminus_imm8()
2485 vassert(rN < 16); in mk_EA_reg_plusminus_reg()
2486 vassert(bU < 2); in mk_EA_reg_plusminus_reg()
2487 vassert(rM < 16); in mk_EA_reg_plusminus_reg()
2578 vassert(imm1 < (1<<1)); in thumbExpandImm()
2579 vassert(imm3 < (1<<3)); in thumbExpandImm()
2580 vassert(imm8 < (1<<8)); in thumbExpandImm()
2602 /*NOTREACHED*/vassert(0); in thumbExpandImm()
2648 vassert(firstcond <= 0xF); in compute_ITSTATE()
2649 vassert(mask <= 0xF); in compute_ITSTATE()
3068 default: vassert(0); in dis_neon_data_3same()
3092 vassert(0); in dis_neon_data_3same()
3109 vassert(0); in dis_neon_data_3same()
3149 vassert(0); in dis_neon_data_3same()
3170 vassert(0); in dis_neon_data_3same()
3202 default: vassert(0); in dis_neon_data_3same()
3221 vassert(0); in dis_neon_data_3same()
3240 vassert(0); in dis_neon_data_3same()
3479 default: vassert(0); in dis_neon_data_3same()
3505 vassert(0); in dis_neon_data_3same()
3522 vassert(0); in dis_neon_data_3same()
3562 vassert(0); in dis_neon_data_3same()
3583 vassert(0); in dis_neon_data_3same()
3609 default: vassert(0); in dis_neon_data_3same()
3617 default: vassert(0); in dis_neon_data_3same()
3654 default: vassert(0); in dis_neon_data_3same()
3676 vassert(0); in dis_neon_data_3same()
3737 vassert(0); in dis_neon_data_3same()
3766 vassert(0); in dis_neon_data_3same()
3844 default: vassert(0); in dis_neon_data_3same()
3876 vassert(0); in dis_neon_data_3same()
3905 vassert(0); in dis_neon_data_3same()
3982 default: vassert(0); in dis_neon_data_3same()
4018 vassert(0); in dis_neon_data_3same()
4051 vassert(0); in dis_neon_data_3same()
4140 default: vassert(0); in dis_neon_data_3same()
4148 default: vassert(0); in dis_neon_data_3same()
4165 default: vassert(0); in dis_neon_data_3same()
4173 default: vassert(0); in dis_neon_data_3same()
4208 vassert(0); in dis_neon_data_3same()
4227 vassert(0); in dis_neon_data_3same()
4277 vassert(0); in dis_neon_data_3same()
4299 vassert(0); in dis_neon_data_3same()
4341 default: vassert(0); in dis_neon_data_3same()
4353 default: vassert(0); in dis_neon_data_3same()
4367 default: vassert(0); in dis_neon_data_3same()
4412 vassert(0); in dis_neon_data_3same()
4431 vassert(0); in dis_neon_data_3same()
4451 default: vassert(0); in dis_neon_data_3same()
4459 default: vassert(0); in dis_neon_data_3same()
4481 default: vassert(0); in dis_neon_data_3same()
4489 default: vassert(0); in dis_neon_data_3same()
4522 vassert(0); in dis_neon_data_3same()
4558 vassert(0); in dis_neon_data_3same()
4585 default: vassert(0); in dis_neon_data_3same()
4651 default: vassert(0); in dis_neon_data_3same()
4660 default: vassert(0); in dis_neon_data_3same()
4851 vassert(0); in dis_neon_data_3diff()
4904 vassert(0); in dis_neon_data_3diff()
4954 vassert(0); in dis_neon_data_3diff()
5014 vassert(0); in dis_neon_data_3diff()
5061 vassert(0); in dis_neon_data_3diff()
5105 vassert(0); in dis_neon_data_3diff()
5143 vassert(0); in dis_neon_data_3diff()
5182 vassert(0); in dis_neon_data_3diff()
5215 vassert(0); in dis_neon_data_3diff()
5281 vassert(0); in dis_neon_data_2reg_and_scalar()
5306 vassert(0); in dis_neon_data_2reg_and_scalar()
5322 vassert(0); in dis_neon_data_2reg_and_scalar()
5340 vassert(0); in dis_neon_data_2reg_and_scalar()
5385 vassert(0); in dis_neon_data_2reg_and_scalar()
5403 vassert(0); in dis_neon_data_2reg_and_scalar()
5444 vassert(0); in dis_neon_data_2reg_and_scalar()
5469 vassert(0); in dis_neon_data_2reg_and_scalar()
5520 vassert(0); in dis_neon_data_2reg_and_scalar()
5545 vassert(0); in dis_neon_data_2reg_and_scalar()
5559 vassert(0); in dis_neon_data_2reg_and_scalar()
5573 vassert(0); in dis_neon_data_2reg_and_scalar()
5615 vassert(0); in dis_neon_data_2reg_and_scalar()
5622 default: vassert(0); in dis_neon_data_2reg_and_scalar()
5659 vassert(0); in dis_neon_data_2reg_and_scalar()
5680 vassert(0); in dis_neon_data_2reg_and_scalar()
5727 vassert(0); in dis_neon_data_2reg_and_scalar()
5752 vassert(0); in dis_neon_data_2reg_and_scalar()
5774 vassert(0); in dis_neon_data_2reg_and_scalar()
5827 vassert(0); in dis_neon_data_2reg_and_scalar()
5852 vassert(0); in dis_neon_data_2reg_and_scalar()
5874 vassert(0); in dis_neon_data_2reg_and_scalar()
5960 vassert(0); in dis_neon_data_2reg_and_shift()
5985 vassert(0); in dis_neon_data_2reg_and_shift()
6010 vassert(0); in dis_neon_data_2reg_and_shift()
6084 vassert(0); in dis_neon_data_2reg_and_shift()
6105 vassert(0); in dis_neon_data_2reg_and_shift()
6145 default: vassert(0); in dis_neon_data_2reg_and_shift()
6194 default: vassert(0); in dis_neon_data_2reg_and_shift()
6240 default: vassert(0); in dis_neon_data_2reg_and_shift()
6279 vassert(0); in dis_neon_data_2reg_and_shift()
6303 vassert(0); in dis_neon_data_2reg_and_shift()
6330 vassert(0); in dis_neon_data_2reg_and_shift()
6387 vassert(0); in dis_neon_data_2reg_and_shift()
6410 default: vassert(0); in dis_neon_data_2reg_and_shift()
6430 vassert(0); in dis_neon_data_2reg_and_shift()
6480 vassert(0); in dis_neon_data_2reg_and_shift()
6485 vassert(U); in dis_neon_data_2reg_and_shift()
6503 vassert(0); in dis_neon_data_2reg_and_shift()
6515 case 0: default: vassert(0); in dis_neon_data_2reg_and_shift()
6521 case 0: default: vassert(0); in dis_neon_data_2reg_and_shift()
6573 vassert(0); in dis_neon_data_2reg_and_shift()
6667 vassert(0); in dis_neon_data_2reg_misc()
6688 vassert(0); in dis_neon_data_2reg_misc()
6707 vassert(0); in dis_neon_data_2reg_misc()
6727 default: vassert(0); in dis_neon_data_2reg_misc()
6735 default: vassert(0); in dis_neon_data_2reg_misc()
6754 default: vassert(0); in dis_neon_data_2reg_misc()
6769 default: vassert(0); in dis_neon_data_2reg_misc()
6813 vassert(0); in dis_neon_data_2reg_misc()
6832 vassert(0); in dis_neon_data_2reg_misc()
6884 vassert(0); in dis_neon_data_2reg_misc()
6937 vassert(0); in dis_neon_data_2reg_misc()
6949 vassert(0); in dis_neon_data_2reg_misc()
6981 default: vassert(0); in dis_neon_data_2reg_misc()
6989 default: vassert(0); in dis_neon_data_2reg_misc()
7010 default: vassert(0); in dis_neon_data_2reg_misc()
7019 default: vassert(0); in dis_neon_data_2reg_misc()
7041 default: vassert(0); in dis_neon_data_2reg_misc()
7050 default: vassert(0); in dis_neon_data_2reg_misc()
7072 default: vassert(0); in dis_neon_data_2reg_misc()
7081 default: vassert(0); in dis_neon_data_2reg_misc()
7103 default: vassert(0); in dis_neon_data_2reg_misc()
7112 default: vassert(0); in dis_neon_data_2reg_misc()
7131 default: vassert(0); in dis_neon_data_2reg_misc()
7151 default: vassert(0); in dis_neon_data_2reg_misc()
7165 default: vassert(0); in dis_neon_data_2reg_misc()
7175 vassert(0); in dis_neon_data_2reg_misc()
7236 vassert(0); in dis_neon_data_2reg_misc()
7255 vassert(0); in dis_neon_data_2reg_misc()
7307 vassert(0); in dis_neon_data_2reg_misc()
7358 vassert(0); in dis_neon_data_2reg_misc()
7381 default: vassert(0); in dis_neon_data_2reg_misc()
7400 default: vassert(0); in dis_neon_data_2reg_misc()
7404 vassert(0); in dis_neon_data_2reg_misc()
7411 default: vassert(0); in dis_neon_data_2reg_misc()
7421 default: vassert(0); in dis_neon_data_2reg_misc()
7431 default: vassert(0); in dis_neon_data_2reg_misc()
7436 vassert(0); in dis_neon_data_2reg_misc()
7463 default: vassert(0); in dis_neon_data_2reg_misc()
7473 vassert(0); // ATC in dis_neon_data_2reg_misc()
7495 vassert(0); in dis_neon_data_2reg_misc()
7562 vassert(0); in dis_neon_data_2reg_misc()
7573 vassert(0); in dis_neon_data_2reg_misc()
7576 vassert(0); in dis_neon_data_2reg_misc()
7636 vassert(0); in ppNeonImmType()
7640 vassert(0); in ppNeonImmType()
7860 vassert(0); in mk_neon_elem_load_to_one_lane()
7895 vassert(0); in mk_neon_elem_load_to_one_lane()
7921 vassert(0); in mk_neon_elem_store_from_one_lane()
7941 vassert(0); in mk_neon_elem_store_from_one_lane()
7963 vassert(condT != IRTemp_INVALID); in dis_neon_load_or_store()
7965 vassert(condT == IRTemp_INVALID); in dis_neon_load_or_store()
7997 default: vassert(0); in dis_neon_load_or_store()
8074 vassert(0); in dis_neon_load_or_store()
8103 vassert(0); in dis_neon_load_or_store()
8289 vassert(condT == IRTemp_INVALID); in decode_NEON_instruction()
8374 vassert(conq == ARMCondAL); in decode_V6MEDIA_instruction()
8376 vassert(INSNA(31,28) == BITS4(0,0,0,0)); // caller's obligation in decode_V6MEDIA_instruction()
8377 vassert(conq >= ARMCondEQ && conq <= ARMCondAL); in decode_V6MEDIA_instruction()
10764 vassert(r != rN); in mk_ldm_stm()
10773 vassert(m == nRegs); in mk_ldm_stm()
10774 vassert(nX == nRegs); in mk_ldm_stm()
10775 vassert(nX <= 16); in mk_ldm_stm()
10788 vassert(nX > 0); in mk_ldm_stm()
10793 vassert(i < nX); /* else we didn't find it! */ in mk_ldm_stm()
10803 vassert(m == nX); in mk_ldm_stm()
10814 vassert(m == -1); in mk_ldm_stm()
10921 vassert(INSN(31,28) == BITS4(0,0,0,0)); // caller's obligation in decode_CP10_CP11_instruction()
10924 vassert(conq == ARMCondAL); in decode_CP10_CP11_instruction()
10926 vassert(conq >= ARMCondEQ && conq <= ARMCondAL); in decode_CP10_CP11_instruction()
11061 default: vassert(0); in decode_CP10_CP11_instruction()
11198 default: vassert(0); in decode_CP10_CP11_instruction()
11504 vassert(0); in decode_CP10_CP11_instruction()
11521 vassert(0); in decode_CP10_CP11_instruction()
11749 vassert(0); in decode_CP10_CP11_instruction()
11947 default: vassert(0); in decode_CP10_CP11_instruction()
12220 vassert(0); in decode_CP10_CP11_instruction()
12414 vassert(INSN(11,9) == BITS3(1,0,1)); // 11:8 = 1010 or 1011 in decode_CP10_CP11_instruction()
12443 vassert(BITS4(1,1,1,1) == INSN_COND); in decode_NV_instruction()
12470 vassert(eaE); in decode_NV_instruction()
12629 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in disInstr_ARM_WRK()
12765 vassert(op == Iop_Sub32); isRSB = True; break; in disInstr_ARM_WRK()
12767 vassert(op == Iop_And32); isBIC = True; break; in disInstr_ARM_WRK()
12783 vassert(op == Iop_Sub32); in disInstr_ARM_WRK()
12787 vassert(op == Iop_And32); in disInstr_ARM_WRK()
12807 vassert(shco == IRTemp_INVALID); in disInstr_ARM_WRK()
12810 vassert(shco != IRTemp_INVALID); in disInstr_ARM_WRK()
12830 vassert(0); in disInstr_ARM_WRK()
12855 vassert(shco != IRTemp_INVALID); in disInstr_ARM_WRK()
12859 vassert(shco == IRTemp_INVALID); in disInstr_ARM_WRK()
12977 vassert(0); in disInstr_ARM_WRK()
12986 vassert(shco == IRTemp_INVALID); in disInstr_ARM_WRK()
12989 vassert(shco != IRTemp_INVALID); in disInstr_ARM_WRK()
13004 vassert(0); in disInstr_ARM_WRK()
13096 vassert(0); in disInstr_ARM_WRK()
13120 vassert(eaE); in disInstr_ARM_WRK()
13134 vassert(taT != IRTemp_INVALID); in disInstr_ARM_WRK()
13161 vassert(bB == 1); in disInstr_ARM_WRK()
13167 vassert(bL == 1); in disInstr_ARM_WRK()
13184 vassert(bB == 1); in disInstr_ARM_WRK()
13194 vassert(rD != rN); /* since we just wrote rD */ in disInstr_ARM_WRK()
13213 default: vassert(0); in disInstr_ARM_WRK()
13329 vassert(0); in disInstr_ARM_WRK()
13352 vassert(eaE); in disInstr_ARM_WRK()
13366 vassert(taT != IRTemp_INVALID); in disInstr_ARM_WRK()
13395 vassert(0); // should be assured by logic above in disInstr_ARM_WRK()
13402 vassert(rD != rN); /* since we just wrote rD */ in disInstr_ARM_WRK()
13416 default: vassert(0); in disInstr_ARM_WRK()
13764 vassert(!isMLS); // guaranteed above in disInstr_ARM_WRK()
13900 vassert(rot <= 30); in disInstr_ARM_WRK()
14032 default: vassert(0); in disInstr_ARM_WRK()
14038 vassert(ty == Ity_I64); in disInstr_ARM_WRK()
14087 default: vassert(0); in disInstr_ARM_WRK()
14094 vassert(ty == Ity_I64); in disInstr_ARM_WRK()
14225 vassert(0); // guarded by "if" above in disInstr_ARM_WRK()
14249 vassert(mask != 0); // guaranteed by "msb < lsb" check above in disInstr_ARM_WRK()
14294 vassert(msb >= 0 && msb <= 31); in disInstr_ARM_WRK()
14295 vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive in disInstr_ARM_WRK()
14401 vassert(0); in disInstr_ARM_WRK()
14424 vassert(eaE); in disInstr_ARM_WRK()
14438 vassert(taT != IRTemp_INVALID); in disInstr_ARM_WRK()
14468 vassert(rD+0 != rN); /* since we just wrote rD+0 */ in disInstr_ARM_WRK()
14469 vassert(rD+1 != rN); /* since we just wrote rD+1 */ in disInstr_ARM_WRK()
14484 default: vassert(0); in disInstr_ARM_WRK()
14752 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in disInstr_ARM_WRK()
14763 vassert(dres.len == 4 || dres.len == 20); in disInstr_ARM_WRK()
14777 vassert(dres.whatNext == Dis_Continue); in disInstr_ARM_WRK()
14778 vassert(irsb->next == NULL); in disInstr_ARM_WRK()
14779 vassert(irsb->jumpkind == Ijk_Boring); in disInstr_ARM_WRK()
14820 vassert(0); in disInstr_ARM_WRK()
14905 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
15014 vassert(guaranteedUnconditional == False); in disInstr_THUMB_WRK()
15017 vassert(0 == (pc & 1)); in disInstr_THUMB_WRK()
15048 vassert(n_guarded >= 1 && n_guarded <= 4); in disInstr_THUMB_WRK()
15082 vassert(old_itstate == IRTemp_INVALID); in disInstr_THUMB_WRK()
15543 /*NOTREACHED*/vassert(0); in disInstr_THUMB_WRK()
15611 vassert(rM == 15); in disInstr_THUMB_WRK()
15803 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
15855 vassert(nRegs >= 1 && nRegs <= 9); in disInstr_THUMB_WRK()
15909 vassert(nRegs >= 0 && nRegs <= 8); in disInstr_THUMB_WRK()
15910 vassert(bitR == 0 || bitR == 1); in disInstr_THUMB_WRK()
16483 /*NOTREACHED*/vassert(0); in disInstr_THUMB_WRK()
16571 vassert(insn1 == 0); in disInstr_THUMB_WRK()
16578 vassert(dres.whatNext == Dis_Continue); in disInstr_THUMB_WRK()
16579 vassert(dres.len == 2); in disInstr_THUMB_WRK()
16580 vassert(dres.continueAt == 0); in disInstr_THUMB_WRK()
16599 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
16918 vassert(0); in disInstr_THUMB_WRK()
16952 default: vassert(0); in disInstr_THUMB_WRK()
17016 default: vassert(0); in disInstr_THUMB_WRK()
17048 vassert(0); in disInstr_THUMB_WRK()
17114 vassert(0); in disInstr_THUMB_WRK()
17150 default: vassert(0); in disInstr_THUMB_WRK()
17171 vassert(op == Iop_And32 || op == Iop_Or32); in disInstr_THUMB_WRK()
17510 vassert(rN != rT); // assured by validity check above in disInstr_THUMB_WRK()
17528 vassert(0); in disInstr_THUMB_WRK()
17546 vassert(0); in disInstr_THUMB_WRK()
17554 vassert(rT == 15); in disInstr_THUMB_WRK()
17562 vassert(rN != rT); // assured by validity check above in disInstr_THUMB_WRK()
17568 vassert(rN != 15); // assured by validity check above in disInstr_THUMB_WRK()
17584 vassert(bP == 0 && bW == 1); in disInstr_THUMB_WRK()
17641 vassert(ty == Ity_I32); in disInstr_THUMB_WRK()
17684 vassert(0); in disInstr_THUMB_WRK()
17697 vassert(0); in disInstr_THUMB_WRK()
17710 vassert(rT == 15); in disInstr_THUMB_WRK()
17777 vassert(ty == Ity_I32); in disInstr_THUMB_WRK()
17804 vassert(ty == Ity_I32 && !isST); in disInstr_THUMB_WRK()
17830 vassert(0); in disInstr_THUMB_WRK()
17843 vassert(0); in disInstr_THUMB_WRK()
17941 vassert(bP == 0 && bW == 1); in disInstr_THUMB_WRK()
17966 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
18010 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
18091 vassert(msb >= 0 && msb <= 31); in disInstr_THUMB_WRK()
18092 vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive in disInstr_THUMB_WRK()
18183 vassert(0); in disInstr_THUMB_WRK()
18372 vassert(mask != 0); // guaranteed by "msb < lsb" check above in disInstr_THUMB_WRK()
18916 vassert(0 == (guest_R15_curr_instr_notENC & 1)); in disInstr_THUMB_WRK()
18925 vassert(dres.len == 4 || dres.len == 2 || dres.len == 20); in disInstr_THUMB_WRK()
18937 vassert(0); in disInstr_THUMB_WRK()
19054 vassert(guest_arch == VexArchARM); in disInstr_ARM()