Lines Matching refs:vassert
71 vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || in ppHRegMIPS()
79 vassert(r >= 0 && r < 32); in ppHRegMIPS()
84 vassert(r >= 0 && r < 32); in ppHRegMIPS()
89 vassert(r >= 0 && r < 32); in ppHRegMIPS()
622 vassert(i == *nregs); in getAllocableRegs_MIPS()
957 vassert(imm16 != 0x8000); in MIPSRH_Imm()
958 vassert(syned == True || syned == False); in MIPSRH_Imm()
1059 vassert(immR == False); /*there's no nor with an immediate operand!? */ in showMIPSAluOp()
1231 vassert(0 == (argiregs & ~mask)); in MIPSInstr_Call()
1245 vassert(0 == (argiregs & ~mask)); in MIPSInstr_CallAlways()
1288 vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); in MIPSInstr_Load()
1291 vassert(mode64); in MIPSInstr_Load()
1302 vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); in MIPSInstr_Store()
1305 vassert(mode64); in MIPSInstr_Store()
1316 vassert(sz == 4 || sz == 8); in MIPSInstr_LoadL()
1319 vassert(mode64); in MIPSInstr_LoadL()
1330 vassert(sz == 4 || sz == 8); in MIPSInstr_StoreC()
1333 vassert(mode64); in MIPSInstr_StoreC()
1387 vassert(sz == 4 || sz == 8); in MIPSInstr_FpLdSt()
1908 vassert(0 == (argir & ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)))); in getRegUsage_MIPSInstr()
2206 vassert(offsetB >= 0); in genSpill_MIPS()
2207 vassert(!hregIsVirtual(rreg)); in genSpill_MIPS()
2213 vassert(mode64); in genSpill_MIPS()
2217 vassert(!mode64); in genSpill_MIPS()
2221 vassert(!mode64); in genSpill_MIPS()
2238 vassert(!hregIsVirtual(rreg)); in genReload_MIPS()
2243 vassert(mode64); in genReload_MIPS()
2247 vassert(!mode64); in genReload_MIPS()
2271 vassert(hregClass(r) == mode64 ? HRcInt64 : HRcInt32); in iregNo()
2272 vassert(!hregIsVirtual(r)); in iregNo()
2274 vassert(n <= 32); in iregNo()
2281 vassert(hregClass(r) == mode64 ? HRcFlt64 : HRcFlt32); in fregNo()
2282 vassert(!hregIsVirtual(r)); in fregNo()
2284 vassert(n <= 31); in fregNo()
2291 vassert(hregClass(r) == HRcFlt64); in dregNo()
2292 vassert(!hregIsVirtual(r)); in dregNo()
2294 vassert(n <= 31); in dregNo()
2341 vassert(opc < 0x40); in mkFormI()
2342 vassert(rs < 0x20); in mkFormI()
2343 vassert(rt < 0x20); in mkFormI()
2362 vassert(opc < 0x40); in mkFormR()
2363 vassert(rs < 0x20); in mkFormR()
2364 vassert(rt < 0x20); in mkFormR()
2365 vassert(rd < 0x20); in mkFormR()
2366 vassert(sa < 0x20); in mkFormR()
2378 vassert(opc1 <= 0x3F); in mkFormS()
2379 vassert(rRD < 0x20); in mkFormS()
2380 vassert(rRS < 0x20); in mkFormS()
2381 vassert(rRT < 0x20); in mkFormS()
2382 vassert(opc2 <= 0x3F); in mkFormS()
2383 vassert(sa >= 0 && sa <= 0x3F); in mkFormS()
2395 vassert(am->tag == Mam_IR); in doAMode_IR()
2396 vassert(am->Mam.IR.index < 0x10000); in doAMode_IR()
2435 vassert(am->tag == Mam_RR); in doAMode_RR()
2492 vassert(r_dst < 0x20); in mkLoadImm()
2512 vassert(mode64); in mkLoadImm()
2537 vassert(r_dst < 0x20); in mkLoadImm_EXACTLY2or5()
2556 vassert(0); in mkLoadImm_EXACTLY2or5()
2566 vassert(r_dst < 0x20); in isLoadImm_EXACTLY2or5()
2584 vassert(p == (UChar*)&expect[2]); in isLoadImm_EXACTLY2or5()
2590 vassert(0); in isLoadImm_EXACTLY2or5()
2606 vassert(0 == (am->Mam.IR.index & 3)); in do_load_or_store_machine_word()
2620 vassert(mode64); in do_load_or_store_machine_word()
2623 vassert(0); in do_load_or_store_machine_word()
2631 vassert(0); in do_load_or_store_machine_word()
2634 vassert(0); in do_load_or_store_machine_word()
2642 vassert(0 == (am->Mam.IR.index & 3)); in do_load_or_store_machine_word()
2655 vassert(mode64); in do_load_or_store_machine_word()
2659 vassert(0); in do_load_or_store_machine_word()
2667 vassert(0); in do_load_or_store_machine_word()
2670 vassert(0); in do_load_or_store_machine_word()
2680 vassert(r_dst < 0x20); in mkMoveReg()
2681 vassert(r_src < 0x20); in mkMoveReg()
2705 vassert(nbuf >= 32); in emit_MIPSInstr()
2748 vassert(srcR->Mrh.Imm.imm16 != 0x8000); in emit_MIPSInstr()
2763 vassert(srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2764 vassert(srcR->Mrh.Imm.imm16 != 0x8000); in emit_MIPSInstr()
2774 vassert(!srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2784 vassert(!srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2806 vassert(!immR); in emit_MIPSInstr()
2812 vassert(!srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2835 vassert(sz32); in emit_MIPSInstr()
2841 vassert(n >= 0 && n < 32); in emit_MIPSInstr()
2850 vassert((n >= 0 && n < 32) || (n > 31 && n < 64)); in emit_MIPSInstr()
2867 vassert(n >= 0 && n < 32); in emit_MIPSInstr()
2877 vassert((n >= 0 && n < 32) || (n > 31 && n < 64)); in emit_MIPSInstr()
2894 vassert(n >= 0 && n < 32); in emit_MIPSInstr()
2904 vassert((n >= 0 && n < 32) || (n > 31 && n < 64)); in emit_MIPSInstr()
3165 vassert(delta >= 20 && delta <= 32); in emit_MIPSInstr()
3168 vassert(cond == MIPScc_EQ); in emit_MIPSInstr()
3181 vassert(disp_cp_chain_me_to_slowEP != NULL); in emit_MIPSInstr()
3182 vassert(disp_cp_chain_me_to_fastEP != NULL); in emit_MIPSInstr()
3191 vassert(i->Min.XDirect.cond != MIPScc_NV); in emit_MIPSInstr()
3226 vassert(delta > 0 && delta < 40); in emit_MIPSInstr()
3244 vassert(disp_cp_xindir != NULL); in emit_MIPSInstr()
3252 vassert(i->Min.XIndir.cond != MIPScc_NV); in emit_MIPSInstr()
3275 vassert(delta > 0 && delta < 40); in emit_MIPSInstr()
3292 vassert(i->Min.XAssisted.cond != MIPScc_NV); in emit_MIPSInstr()
3328 vassert(trcval != 0); in emit_MIPSInstr()
3343 vassert(delta > 0 && delta < 40); in emit_MIPSInstr()
3361 vassert(0 == (am_addr->Mam.IR.index & 3)); in emit_MIPSInstr()
3375 vassert(mode64); in emit_MIPSInstr()
3399 vassert(mode64); in emit_MIPSInstr()
3418 vassert(0 == (am_addr->Mam.IR.index & 3)); in emit_MIPSInstr()
3431 vassert(mode64); in emit_MIPSInstr()
3455 vassert(mode64); in emit_MIPSInstr()
3500 vassert(sz == 4 || sz == 8); in emit_MIPSInstr()
3850 vassert(evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0); in emit_MIPSInstr()
3871 vassert(0); in emit_MIPSInstr()
3899 vassert(!(*is_profInc)); in emit_MIPSInstr()
3944 vassert(0 == (3 & (HWord)p)); in chainXDirect_MIPS()
3945 vassert(isLoadImm_EXACTLY2or5(p, /*r*/9, in chainXDirect_MIPS()
3948 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x120F809); in chainXDirect_MIPS()
3949 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x00000000); in chainXDirect_MIPS()
3968 vassert(len == (mode64 ? 28 : 16)); /* stay sane */ in chainXDirect_MIPS()
3990 vassert(0 == (3 & (HWord)p)); in unchainXDirect_MIPS()
3991 vassert(isLoadImm_EXACTLY2or5(p, /*r*/9, in unchainXDirect_MIPS()
3994 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x120F809); in unchainXDirect_MIPS()
3995 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x00000000); in unchainXDirect_MIPS()
4012 vassert(len == (mode64 ? 28 : 16)); /* stay sane */ in unchainXDirect_MIPS()
4022 vassert(sizeof(ULong*) == 4); in patchProfInc_MIPS()
4024 vassert(0 == (3 & (HWord)p)); in patchProfInc_MIPS()
4025 vassert(isLoadImm_EXACTLY2or5((UChar *)p, /*r*/9, 0x65556555, mode64)); in patchProfInc_MIPS()
4027 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x8D280000); in patchProfInc_MIPS()
4028 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x25080001); in patchProfInc_MIPS()
4029 vassert(fetch32(p + (mode64 ? 20 : 8) + 8) == 0xAD280000); in patchProfInc_MIPS()
4030 vassert(fetch32(p + (mode64 ? 20 : 8) + 12) == 0x2d010001); in patchProfInc_MIPS()
4031 vassert(fetch32(p + (mode64 ? 20 : 8) + 16) == 0x8d280004); in patchProfInc_MIPS()
4032 vassert(fetch32(p + (mode64 ? 20 : 8) + 20) == 0x01014021); in patchProfInc_MIPS()
4033 vassert(fetch32(p + (mode64 ? 20 : 8) + 24) == 0xad280004); in patchProfInc_MIPS()