62 Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* LLc)  in Intel_cache_info()  argument
126       case 0x0a: *D1c = (cache_t) {  8, 2, 32 }; break;  in Intel_cache_info()
127       case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break;  in Intel_cache_info()
128       case 0x0d: *D1c = (cache_t) { 16, 4, 64 }; break;  in Intel_cache_info()
129       case 0x0e: *D1c = (cache_t) { 24, 6, 64 }; break;  in Intel_cache_info()
130       case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break;  in Intel_cache_info()
196       case 0x60: *D1c = (cache_t) { 16, 8, 64 };  break;      /* sectored */  in Intel_cache_info()
197       case 0x66: *D1c = (cache_t) {  8, 4, 64 };  break;      /* sectored */  in Intel_cache_info()
198       case 0x67: *D1c = (cache_t) { 16, 4, 64 };  break;      /* sectored */  in Intel_cache_info()
199       case 0x68: *D1c = (cache_t) { 32, 4, 64 };  break;      /* sectored */  in Intel_cache_info()
264                case 1: *D1c = c; break;  in Intel_cache_info()
366 Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* LLc)  in AMD_cache_info()  argument
391    D1c->size      = (D1i >> 24) & 0xff;  in AMD_cache_info()
392    D1c->assoc     = (D1i >> 16) & 0xff;  in AMD_cache_info()
393    D1c->line_size = (D1i >>  0) & 0xff;  in AMD_cache_info()
418 Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* LLc)  in get_caches_from_CPUID()  argument
439       ret = Intel_cache_info(level, I1c, D1c, LLc);  in get_caches_from_CPUID()
442       ret = AMD_cache_info(I1c, D1c, LLc);  in get_caches_from_CPUID()
446       D1c->size      = 64;  in get_caches_from_CPUID()
447       D1c->assoc     = 16;  in get_caches_from_CPUID()
448       D1c->line_size = 16;  in get_caches_from_CPUID()
464    D1c->size *= 1024;  in get_caches_from_CPUID()
524 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,  in VG_()
531    *D1c = (cache_t) {  65536, 2, 64 };  in VG_()
535    res = get_caches_from_CPUID(I1c, D1c, LLc);  in VG_()