Lines Matching refs:CLG_
113 Addr CLG_(bb_base);
114 ULong* CLG_(cost_base);
847 idx, CLG_(bb_base) + current_ii->instr_offset, memline); in update_LL_use()
852 CLG_(current_state).collect, loaded->use_base); in update_LL_use()
854 if (CLG_(current_state).collect && loaded->use_base) { in update_LL_use()
864 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; in update_LL_use()
865 loaded->use_base = (CLG_(current_state).nonskipped) ? in update_LL_use()
866 CLG_(current_state).nonskipped->skipped : in update_LL_use()
867 CLG_(cost_base) + current_ii->cost_offset; in update_LL_use()
935 cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
940 CLG_(current_state).collect, loaded->use_base); \
942 if (CLG_(current_state).collect && loaded->use_base) { \
955 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \
956 loaded->use_base = (CLG_(current_state).nonskipped) ? \
957 CLG_(current_state).nonskipped->skipped : \
958 CLG_(cost_base) + current_ii->cost_offset; \
977 if (!CLG_(current_state).collect) return; in cacheuse_finish()
979 CLG_(bb_base) = 0; in cacheuse_finish()
981 CLG_(cost_base) = 0; in cacheuse_finish()
1056 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I0D()
1059 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes)); in log_1I0D()
1061 if (CLG_(current_state).collect) { in log_1I0D()
1064 if (CLG_(current_state).nonskipped) in log_1I0D()
1065 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I0D()
1067 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I0D()
1070 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I0D()
1081 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_2I0D()
1083 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_2I0D()
1086 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), in log_2I0D()
1087 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) ); in log_2I0D()
1089 if (!CLG_(current_state).collect) return; in log_2I0D()
1091 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); in log_2I0D()
1092 if (CLG_(current_state).nonskipped) { in log_2I0D()
1094 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_2I0D()
1102 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); in log_2I0D()
1104 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); in log_2I0D()
1114 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_3I0D()
1116 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_3I0D()
1118 Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size); in log_3I0D()
1121 CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), in log_3I0D()
1122 CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res), in log_3I0D()
1123 CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) ); in log_3I0D()
1125 if (!CLG_(current_state).collect) return; in log_3I0D()
1127 global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); in log_3I0D()
1128 if (CLG_(current_state).nonskipped) { in log_3I0D()
1130 CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_3I0D()
1138 CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); in log_3I0D()
1140 CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); in log_3I0D()
1142 CLG_(cost_base) + ii3->cost_offset + ii3->eventset->offset[EG_IR]); in log_3I0D()
1153 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dr()
1157 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), in log_1I1Dr()
1160 if (CLG_(current_state).collect) { in log_1I1Dr()
1163 if (CLG_(current_state).nonskipped) { in log_1I1Dr()
1164 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I1Dr()
1165 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); in log_1I1Dr()
1168 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I1Dr()
1169 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; in log_1I1Dr()
1173 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I1Dr()
1175 CLG_(current_state).cost + fullOffset(EG_DR) ); in log_1I1Dr()
1191 if (CLG_(current_state).collect) { in log_0I1Dr()
1194 if (CLG_(current_state).nonskipped) in log_0I1Dr()
1195 cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); in log_0I1Dr()
1197 cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; in log_0I1Dr()
1200 CLG_(current_state).cost + fullOffset(EG_DR) ); in log_0I1Dr()
1213 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dw()
1217 CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), in log_1I1Dw()
1220 if (CLG_(current_state).collect) { in log_1I1Dw()
1223 if (CLG_(current_state).nonskipped) { in log_1I1Dw()
1224 cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); in log_1I1Dw()
1225 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); in log_1I1Dw()
1228 cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; in log_1I1Dw()
1229 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; in log_1I1Dw()
1233 CLG_(current_state).cost + fullOffset(EG_IR) ); in log_1I1Dw()
1235 CLG_(current_state).cost + fullOffset(EG_DW) ); in log_1I1Dw()
1250 if (CLG_(current_state).collect) { in log_0I1Dw()
1253 if (CLG_(current_state).nonskipped) in log_0I1Dw()
1254 cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); in log_0I1Dw()
1256 cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; in log_0I1Dw()
1259 CLG_(current_state).cost + fullOffset(EG_DW) ); in log_0I1Dw()
1280 if (!CLG_(clo).simulate_cache) { in cachesim_post_clo_init()
1281 CLG_(cachesim).log_1I0D = 0; in cachesim_post_clo_init()
1282 CLG_(cachesim).log_1I0D_name = "(no function)"; in cachesim_post_clo_init()
1283 CLG_(cachesim).log_2I0D = 0; in cachesim_post_clo_init()
1284 CLG_(cachesim).log_2I0D_name = "(no function)"; in cachesim_post_clo_init()
1285 CLG_(cachesim).log_3I0D = 0; in cachesim_post_clo_init()
1286 CLG_(cachesim).log_3I0D_name = "(no function)"; in cachesim_post_clo_init()
1288 CLG_(cachesim).log_1I1Dr = 0; in cachesim_post_clo_init()
1289 CLG_(cachesim).log_1I1Dr_name = "(no function)"; in cachesim_post_clo_init()
1290 CLG_(cachesim).log_1I1Dw = 0; in cachesim_post_clo_init()
1291 CLG_(cachesim).log_1I1Dw_name = "(no function)"; in cachesim_post_clo_init()
1293 CLG_(cachesim).log_0I1Dr = 0; in cachesim_post_clo_init()
1294 CLG_(cachesim).log_0I1Dr_name = "(no function)"; in cachesim_post_clo_init()
1295 CLG_(cachesim).log_0I1Dw = 0; in cachesim_post_clo_init()
1296 CLG_(cachesim).log_0I1Dw_name = "(no function)"; in cachesim_post_clo_init()
1313 CLG_(min_line_size) = (I1c.line_size < D1c.line_size) in cachesim_post_clo_init()
1315 CLG_(min_line_size) = (LLc.line_size < CLG_(min_line_size)) in cachesim_post_clo_init()
1316 ? LLc.line_size : CLG_(min_line_size); in cachesim_post_clo_init()
1320 if (CLG_(min_line_size) < largest_load_or_store_size) { in cachesim_post_clo_init()
1325 (Int)CLG_(min_line_size)); in cachesim_post_clo_init()
1339 CLG_(cachesim).log_1I0D = log_1I0D; in cachesim_post_clo_init()
1340 CLG_(cachesim).log_1I0D_name = "log_1I0D"; in cachesim_post_clo_init()
1341 CLG_(cachesim).log_2I0D = log_2I0D; in cachesim_post_clo_init()
1342 CLG_(cachesim).log_2I0D_name = "log_2I0D"; in cachesim_post_clo_init()
1343 CLG_(cachesim).log_3I0D = log_3I0D; in cachesim_post_clo_init()
1344 CLG_(cachesim).log_3I0D_name = "log_3I0D"; in cachesim_post_clo_init()
1346 CLG_(cachesim).log_1I1Dr = log_1I1Dr; in cachesim_post_clo_init()
1347 CLG_(cachesim).log_1I1Dw = log_1I1Dw; in cachesim_post_clo_init()
1348 CLG_(cachesim).log_1I1Dr_name = "log_1I1Dr"; in cachesim_post_clo_init()
1349 CLG_(cachesim).log_1I1Dw_name = "log_1I1Dw"; in cachesim_post_clo_init()
1351 CLG_(cachesim).log_0I1Dr = log_0I1Dr; in cachesim_post_clo_init()
1352 CLG_(cachesim).log_0I1Dw = log_0I1Dw; in cachesim_post_clo_init()
1353 CLG_(cachesim).log_0I1Dr_name = "log_0I1Dr"; in cachesim_post_clo_init()
1354 CLG_(cachesim).log_0I1Dw_name = "log_0I1Dw"; in cachesim_post_clo_init()
1457 CLG_(clo).dump_instr = True; in cachesim_parse_opt()
1523 FullCost total = CLG_(total_cost), D_total = 0; in cachesim_printstat()
1563 D_total = CLG_(get_eventset_cost)( CLG_(sets).full ); in cachesim_printstat()
1564 CLG_(init_cost)( CLG_(sets).full, D_total); in cachesim_printstat()
1566 CLG_(copy_cost)( CLG_(get_event_set)(EG_DR), D_total, total + fullOffset(EG_DR) ); in cachesim_printstat()
1567 CLG_(add_cost) ( CLG_(get_event_set)(EG_DW), D_total, total + fullOffset(EG_DW) ); in cachesim_printstat()
1658 struct event_sets CLG_(sets);
1660 void CLG_(init_eventsets)() in CLG_() function
1665 CLG_(register_event_group4)(EG_USE, in CLG_()
1668 if (!CLG_(clo).simulate_cache) in CLG_()
1669 CLG_(register_event_group)(EG_IR, "Ir"); in CLG_()
1671 CLG_(register_event_group3)(EG_IR, "Ir", "I1mr", "ILmr"); in CLG_()
1672 CLG_(register_event_group3)(EG_DR, "Dr", "D1mr", "DLmr"); in CLG_()
1673 CLG_(register_event_group3)(EG_DW, "Dw", "D1mw", "DLmw"); in CLG_()
1676 CLG_(register_event_group4)(EG_IR, "Ir", "I1mr", "ILmr", "ILdmr"); in CLG_()
1677 CLG_(register_event_group4)(EG_DR, "Dr", "D1mr", "DLmr", "DLdmr"); in CLG_()
1678 CLG_(register_event_group4)(EG_DW, "Dw", "D1mw", "DLmw", "DLdmw"); in CLG_()
1681 if (CLG_(clo).simulate_branch) { in CLG_()
1682 CLG_(register_event_group2)(EG_BC, "Bc", "Bcm"); in CLG_()
1683 CLG_(register_event_group2)(EG_BI, "Bi", "Bim"); in CLG_()
1686 if (CLG_(clo).collect_bus) in CLG_()
1687 CLG_(register_event_group)(EG_BUS, "Ge"); in CLG_()
1689 if (CLG_(clo).collect_alloc) in CLG_()
1690 CLG_(register_event_group2)(EG_ALLOC, "allocCount", "allocSize"); in CLG_()
1692 if (CLG_(clo).collect_systime) in CLG_()
1693 CLG_(register_event_group2)(EG_SYS, "sysCount", "sysTime"); in CLG_()
1696 CLG_(sets).base = CLG_(get_event_set2)(EG_USE, EG_IR); in CLG_()
1699 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).base, EG_DR, EG_DW); in CLG_()
1700 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_BC, EG_BI); in CLG_()
1701 CLG_(sets).full = CLG_(add_event_group) (CLG_(sets).full, EG_BUS); in CLG_()
1702 CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_ALLOC, EG_SYS); in CLG_()
1706 CLG_(print_eventset)(-2, CLG_(sets).base); in CLG_()
1707 CLG_(print_eventset)(-2, CLG_(sets).full); in CLG_()
1711 CLG_(dumpmap) = CLG_(get_eventmapping)(CLG_(sets).full); in CLG_()
1712 CLG_(append_event)(CLG_(dumpmap), "Ir"); in CLG_()
1713 CLG_(append_event)(CLG_(dumpmap), "Dr"); in CLG_()
1714 CLG_(append_event)(CLG_(dumpmap), "Dw"); in CLG_()
1715 CLG_(append_event)(CLG_(dumpmap), "I1mr"); in CLG_()
1716 CLG_(append_event)(CLG_(dumpmap), "D1mr"); in CLG_()
1717 CLG_(append_event)(CLG_(dumpmap), "D1mw"); in CLG_()
1718 CLG_(append_event)(CLG_(dumpmap), "ILmr"); in CLG_()
1719 CLG_(append_event)(CLG_(dumpmap), "DLmr"); in CLG_()
1720 CLG_(append_event)(CLG_(dumpmap), "DLmw"); in CLG_()
1721 CLG_(append_event)(CLG_(dumpmap), "ILdmr"); in CLG_()
1722 CLG_(append_event)(CLG_(dumpmap), "DLdmr"); in CLG_()
1723 CLG_(append_event)(CLG_(dumpmap), "DLdmw"); in CLG_()
1724 CLG_(append_event)(CLG_(dumpmap), "Bc"); in CLG_()
1725 CLG_(append_event)(CLG_(dumpmap), "Bcm"); in CLG_()
1726 CLG_(append_event)(CLG_(dumpmap), "Bi"); in CLG_()
1727 CLG_(append_event)(CLG_(dumpmap), "Bim"); in CLG_()
1728 CLG_(append_event)(CLG_(dumpmap), "AcCost1"); in CLG_()
1729 CLG_(append_event)(CLG_(dumpmap), "SpLoss1"); in CLG_()
1730 CLG_(append_event)(CLG_(dumpmap), "AcCost2"); in CLG_()
1731 CLG_(append_event)(CLG_(dumpmap), "SpLoss2"); in CLG_()
1732 CLG_(append_event)(CLG_(dumpmap), "Ge"); in CLG_()
1733 CLG_(append_event)(CLG_(dumpmap), "allocCount"); in CLG_()
1734 CLG_(append_event)(CLG_(dumpmap), "allocSize"); in CLG_()
1735 CLG_(append_event)(CLG_(dumpmap), "sysCount"); in CLG_()
1736 CLG_(append_event)(CLG_(dumpmap), "sysTime"); in CLG_()
1744 if (!CLG_(clo).simulate_cache) in cachesim_add_icost()
1748 CLG_(add_and_zero_cost2)( CLG_(sets).full, cost, in cachesim_add_icost()
1763 struct cachesim_if CLG_(cachesim) = {