Lines Matching refs:set1
279 UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1); in cachesim_ref() local
284 if (set1 == set2) in cachesim_ref()
285 return cachesim_setref(c, set1, tag); in cachesim_ref()
289 else if (((set1 + 1) & (c->sets_min_1)) == set2) { in cachesim_ref()
293 CacheResult res1 = cachesim_setref(c, set1, tag); in cachesim_ref()
298 VG_(printf)("addr: %lx size: %u sets: %d %d", a, size, set1, set2); in cachesim_ref()
383 UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1); in cachesim_ref_wb() local
388 if (set1 == set2) in cachesim_ref_wb()
389 return cachesim_setref_wb(c, ref, set1, tag); in cachesim_ref_wb()
393 else if (((set1 + 1) & (c->sets_min_1)) == set2) { in cachesim_ref_wb()
397 CacheResult res1 = cachesim_setref_wb(c, ref, set1, tag); in cachesim_ref_wb()
404 VG_(printf)("addr: %lx size: %u sets: %d %d", a, size, set1, set2); in cachesim_ref_wb()
677 UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \
686 L.name, a, size, set1, set2); \
689 if (set1 == set2) { \
691 set = &(L.tags[set1 * L.assoc]); \
699 idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
716 idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
732 idx = (set1 * L.assoc) + tmp_tag; \
738 } else if (((set1 + 1) & (L.sets_min_1)) == set2) { \
740 set = &(L.tags[set1 * L.assoc]); \
743 idx = (set1 * L.assoc) + (set[0] & ~L.tag_mask); \
758 idx = (set1 * L.assoc) + (tmp_tag & ~L.tag_mask); \
772 idx = (set1 * L.assoc) + tmp_tag; \
815 VG_(printf)("addr: %#lx size: %u sets: %d %d", a, size, set1, set2); \