1 //===-- AMDILDeviceInfo.h - Constants for describing devices --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //==-----------------------------------------------------------------------===// 10 #ifndef AMDILDEVICEINFO_H 11 #define AMDILDEVICEINFO_H 12 13 14 #include <string> 15 16 namespace llvm { 17 class AMDGPUDevice; 18 class AMDGPUSubtarget; 19 namespace AMDGPUDeviceInfo { 20 /// Each Capabilities can be executed using a hardware instruction, 21 /// emulated with a sequence of software instructions, or not 22 /// supported at all. 23 enum ExecutionMode { 24 Unsupported = 0, ///< Unsupported feature on the card(Default value) 25 /// This is the execution mode that is set if the feature is emulated in 26 /// software. 27 Software, 28 /// This execution mode is set if the feature exists natively in hardware 29 Hardware 30 }; 31 32 enum Caps { 33 HalfOps = 0x1, ///< Half float is supported or not. 34 DoubleOps = 0x2, ///< Double is supported or not. 35 ByteOps = 0x3, ///< Byte(char) is support or not. 36 ShortOps = 0x4, ///< Short is supported or not. 37 LongOps = 0x5, ///< Long is supported or not. 38 Images = 0x6, ///< Images are supported or not. 39 ByteStores = 0x7, ///< ByteStores available(!HD4XXX). 40 ConstantMem = 0x8, ///< Constant/CB memory. 41 LocalMem = 0x9, ///< Local/LDS memory. 42 PrivateMem = 0xA, ///< Scratch/Private/Stack memory. 43 RegionMem = 0xB, ///< OCL GDS Memory Extension. 44 FMA = 0xC, ///< Use HW FMA or SW FMA. 45 ArenaSegment = 0xD, ///< Use for Arena UAV per pointer 12-1023. 46 MultiUAV = 0xE, ///< Use for UAV per Pointer 0-7. 47 Reserved0 = 0xF, ///< ReservedFlag 48 NoAlias = 0x10, ///< Cached loads. 49 Signed24BitOps = 0x11, ///< Peephole Optimization. 50 /// Debug mode implies that no hardware features or optimizations 51 /// are performned and that all memory access go through a single 52 /// uav(Arena on HD5XXX/HD6XXX and Raw on HD4XXX). 53 Debug = 0x12, 54 CachedMem = 0x13, ///< Cached mem is available or not. 55 BarrierDetect = 0x14, ///< Detect duplicate barriers. 56 Reserved1 = 0x15, ///< Reserved flag 57 ByteLDSOps = 0x16, ///< Flag to specify if byte LDS ops are available. 58 ArenaVectors = 0x17, ///< Flag to specify if vector loads from arena work. 59 TmrReg = 0x18, ///< Flag to specify if Tmr register is supported. 60 NoInline = 0x19, ///< Flag to specify that no inlining should occur. 61 MacroDB = 0x1A, ///< Flag to specify that backend handles macrodb. 62 HW64BitDivMod = 0x1B, ///< Flag for backend to generate 64bit div/mod. 63 ArenaUAV = 0x1C, ///< Flag to specify that arena uav is supported. 64 PrivateUAV = 0x1D, ///< Flag to specify that private memory uses uav's. 65 /// If more capabilities are required, then 66 /// this number needs to be increased. 67 /// All capabilities must come before this 68 /// number. 69 MaxNumberCapabilities = 0x20 70 }; 71 /// These have to be in order with the older generations 72 /// having the lower number enumerations. 73 enum Generation { 74 HD4XXX = 0, ///< 7XX based devices. 75 HD5XXX, ///< Evergreen based devices. 76 HD6XXX, ///< NI/Evergreen+ based devices. 77 HD7XXX, ///< Southern Islands based devices. 78 HDTEST, ///< Experimental feature testing device. 79 HDNUMGEN 80 }; 81 82 83 AMDGPUDevice* 84 getDeviceFromName(const std::string &name, AMDGPUSubtarget *ptr, 85 bool is64bit = false, bool is64on32bit = false); 86 } // namespace AMDILDeviceInfo 87 } // namespace llvm 88 #endif // AMDILDEVICEINFO_H 89