• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 #define GET_INSTRINFO_CTOR
34 #include "PPCGenInstrInfo.inc"
35 
36 using namespace llvm;
37 
38 static cl::
39 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
40             cl::desc("Disable analysis for CTR loops"));
41 
PPCInstrInfo(PPCTargetMachine & tm)42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43   : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
45 
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
CreateTargetHazardRecognizer(const TargetMachine * TM,const ScheduleDAG * DAG) const48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49   const TargetMachine *TM,
50   const ScheduleDAG *DAG) const {
51   unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
52   if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
53       Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
54     const InstrItineraryData *II = TM->getInstrItineraryData();
55     return new PPCScoreboardHazardRecognizer(II, DAG);
56   }
57 
58   return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
59 }
60 
61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
62 /// to use for this target when scheduling the DAG.
CreateTargetPostRAHazardRecognizer(const InstrItineraryData * II,const ScheduleDAG * DAG) const63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
64   const InstrItineraryData *II,
65   const ScheduleDAG *DAG) const {
66   unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
67 
68   // Most subtargets use a PPC970 recognizer.
69   if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
70       Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
71     const TargetInstrInfo *TII = TM.getInstrInfo();
72     assert(TII && "No InstrInfo?");
73 
74     return new PPCHazardRecognizer970(*TII);
75   }
76 
77   return new PPCScoreboardHazardRecognizer(II, DAG);
78 }
79 
80 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
isCoalescableExtInstr(const MachineInstr & MI,unsigned & SrcReg,unsigned & DstReg,unsigned & SubIdx) const81 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
82                                          unsigned &SrcReg, unsigned &DstReg,
83                                          unsigned &SubIdx) const {
84   switch (MI.getOpcode()) {
85   default: return false;
86   case PPC::EXTSW:
87   case PPC::EXTSW_32_64:
88     SrcReg = MI.getOperand(1).getReg();
89     DstReg = MI.getOperand(0).getReg();
90     SubIdx = PPC::sub_32;
91     return true;
92   }
93 }
94 
isLoadFromStackSlot(const MachineInstr * MI,int & FrameIndex) const95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                            int &FrameIndex) const {
97   switch (MI->getOpcode()) {
98   default: break;
99   case PPC::LD:
100   case PPC::LWZ:
101   case PPC::LFS:
102   case PPC::LFD:
103     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104         MI->getOperand(2).isFI()) {
105       FrameIndex = MI->getOperand(2).getIndex();
106       return MI->getOperand(0).getReg();
107     }
108     break;
109   }
110   return 0;
111 }
112 
isStoreToStackSlot(const MachineInstr * MI,int & FrameIndex) const113 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114                                           int &FrameIndex) const {
115   switch (MI->getOpcode()) {
116   default: break;
117   case PPC::STD:
118   case PPC::STW:
119   case PPC::STFS:
120   case PPC::STFD:
121     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122         MI->getOperand(2).isFI()) {
123       FrameIndex = MI->getOperand(2).getIndex();
124       return MI->getOperand(0).getReg();
125     }
126     break;
127   }
128   return 0;
129 }
130 
131 // commuteInstruction - We can commute rlwimi instructions, but only if the
132 // rotate amt is zero.  We also have to munge the immediates a bit.
133 MachineInstr *
commuteInstruction(MachineInstr * MI,bool NewMI) const134 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135   MachineFunction &MF = *MI->getParent()->getParent();
136 
137   // Normal instructions can be commuted the obvious way.
138   if (MI->getOpcode() != PPC::RLWIMI)
139     return TargetInstrInfo::commuteInstruction(MI, NewMI);
140 
141   // Cannot commute if it has a non-zero rotate count.
142   if (MI->getOperand(3).getImm() != 0)
143     return 0;
144 
145   // If we have a zero rotate count, we have:
146   //   M = mask(MB,ME)
147   //   Op0 = (Op1 & ~M) | (Op2 & M)
148   // Change this to:
149   //   M = mask((ME+1)&31, (MB-1)&31)
150   //   Op0 = (Op2 & ~M) | (Op1 & M)
151 
152   // Swap op1/op2
153   unsigned Reg0 = MI->getOperand(0).getReg();
154   unsigned Reg1 = MI->getOperand(1).getReg();
155   unsigned Reg2 = MI->getOperand(2).getReg();
156   bool Reg1IsKill = MI->getOperand(1).isKill();
157   bool Reg2IsKill = MI->getOperand(2).isKill();
158   bool ChangeReg0 = false;
159   // If machine instrs are no longer in two-address forms, update
160   // destination register as well.
161   if (Reg0 == Reg1) {
162     // Must be two address instruction!
163     assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
164            "Expecting a two-address instruction!");
165     Reg2IsKill = false;
166     ChangeReg0 = true;
167   }
168 
169   // Masks.
170   unsigned MB = MI->getOperand(4).getImm();
171   unsigned ME = MI->getOperand(5).getImm();
172 
173   if (NewMI) {
174     // Create a new instruction.
175     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176     bool Reg0IsDead = MI->getOperand(0).isDead();
177     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178       .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
179       .addReg(Reg2, getKillRegState(Reg2IsKill))
180       .addReg(Reg1, getKillRegState(Reg1IsKill))
181       .addImm((ME+1) & 31)
182       .addImm((MB-1) & 31);
183   }
184 
185   if (ChangeReg0)
186     MI->getOperand(0).setReg(Reg2);
187   MI->getOperand(2).setReg(Reg1);
188   MI->getOperand(1).setReg(Reg2);
189   MI->getOperand(2).setIsKill(Reg1IsKill);
190   MI->getOperand(1).setIsKill(Reg2IsKill);
191 
192   // Swap the mask around.
193   MI->getOperand(4).setImm((ME+1) & 31);
194   MI->getOperand(5).setImm((MB-1) & 31);
195   return MI;
196 }
197 
insertNoop(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI) const198 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199                               MachineBasicBlock::iterator MI) const {
200   DebugLoc DL;
201   BuildMI(MBB, MI, DL, get(PPC::NOP));
202 }
203 
204 
205 // Branch analysis.
206 // Note: If the condition register is set to CTR or CTR8 then this is a
207 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const208 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209                                  MachineBasicBlock *&FBB,
210                                  SmallVectorImpl<MachineOperand> &Cond,
211                                  bool AllowModify) const {
212   bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
213 
214   // If the block has no terminators, it just falls into the block after it.
215   MachineBasicBlock::iterator I = MBB.end();
216   if (I == MBB.begin())
217     return false;
218   --I;
219   while (I->isDebugValue()) {
220     if (I == MBB.begin())
221       return false;
222     --I;
223   }
224   if (!isUnpredicatedTerminator(I))
225     return false;
226 
227   // Get the last instruction in the block.
228   MachineInstr *LastInst = I;
229 
230   // If there is only one terminator instruction, process it.
231   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
232     if (LastInst->getOpcode() == PPC::B) {
233       if (!LastInst->getOperand(0).isMBB())
234         return true;
235       TBB = LastInst->getOperand(0).getMBB();
236       return false;
237     } else if (LastInst->getOpcode() == PPC::BCC) {
238       if (!LastInst->getOperand(2).isMBB())
239         return true;
240       // Block ends with fall-through condbranch.
241       TBB = LastInst->getOperand(2).getMBB();
242       Cond.push_back(LastInst->getOperand(0));
243       Cond.push_back(LastInst->getOperand(1));
244       return false;
245     } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
246                LastInst->getOpcode() == PPC::BDNZ) {
247       if (!LastInst->getOperand(0).isMBB())
248         return true;
249       if (DisableCTRLoopAnal)
250         return true;
251       TBB = LastInst->getOperand(0).getMBB();
252       Cond.push_back(MachineOperand::CreateImm(1));
253       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
254                                                true));
255       return false;
256     } else if (LastInst->getOpcode() == PPC::BDZ8 ||
257                LastInst->getOpcode() == PPC::BDZ) {
258       if (!LastInst->getOperand(0).isMBB())
259         return true;
260       if (DisableCTRLoopAnal)
261         return true;
262       TBB = LastInst->getOperand(0).getMBB();
263       Cond.push_back(MachineOperand::CreateImm(0));
264       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
265                                                true));
266       return false;
267     }
268 
269     // Otherwise, don't know what this is.
270     return true;
271   }
272 
273   // Get the instruction before it if it's a terminator.
274   MachineInstr *SecondLastInst = I;
275 
276   // If there are three terminators, we don't know what sort of block this is.
277   if (SecondLastInst && I != MBB.begin() &&
278       isUnpredicatedTerminator(--I))
279     return true;
280 
281   // If the block ends with PPC::B and PPC:BCC, handle it.
282   if (SecondLastInst->getOpcode() == PPC::BCC &&
283       LastInst->getOpcode() == PPC::B) {
284     if (!SecondLastInst->getOperand(2).isMBB() ||
285         !LastInst->getOperand(0).isMBB())
286       return true;
287     TBB =  SecondLastInst->getOperand(2).getMBB();
288     Cond.push_back(SecondLastInst->getOperand(0));
289     Cond.push_back(SecondLastInst->getOperand(1));
290     FBB = LastInst->getOperand(0).getMBB();
291     return false;
292   } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
293               SecondLastInst->getOpcode() == PPC::BDNZ) &&
294       LastInst->getOpcode() == PPC::B) {
295     if (!SecondLastInst->getOperand(0).isMBB() ||
296         !LastInst->getOperand(0).isMBB())
297       return true;
298     if (DisableCTRLoopAnal)
299       return true;
300     TBB = SecondLastInst->getOperand(0).getMBB();
301     Cond.push_back(MachineOperand::CreateImm(1));
302     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
303                                              true));
304     FBB = LastInst->getOperand(0).getMBB();
305     return false;
306   } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
307               SecondLastInst->getOpcode() == PPC::BDZ) &&
308       LastInst->getOpcode() == PPC::B) {
309     if (!SecondLastInst->getOperand(0).isMBB() ||
310         !LastInst->getOperand(0).isMBB())
311       return true;
312     if (DisableCTRLoopAnal)
313       return true;
314     TBB = SecondLastInst->getOperand(0).getMBB();
315     Cond.push_back(MachineOperand::CreateImm(0));
316     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
317                                              true));
318     FBB = LastInst->getOperand(0).getMBB();
319     return false;
320   }
321 
322   // If the block ends with two PPC:Bs, handle it.  The second one is not
323   // executed, so remove it.
324   if (SecondLastInst->getOpcode() == PPC::B &&
325       LastInst->getOpcode() == PPC::B) {
326     if (!SecondLastInst->getOperand(0).isMBB())
327       return true;
328     TBB = SecondLastInst->getOperand(0).getMBB();
329     I = LastInst;
330     if (AllowModify)
331       I->eraseFromParent();
332     return false;
333   }
334 
335   // Otherwise, can't handle this.
336   return true;
337 }
338 
RemoveBranch(MachineBasicBlock & MBB) const339 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
340   MachineBasicBlock::iterator I = MBB.end();
341   if (I == MBB.begin()) return 0;
342   --I;
343   while (I->isDebugValue()) {
344     if (I == MBB.begin())
345       return 0;
346     --I;
347   }
348   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
349       I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
350       I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
351     return 0;
352 
353   // Remove the branch.
354   I->eraseFromParent();
355 
356   I = MBB.end();
357 
358   if (I == MBB.begin()) return 1;
359   --I;
360   if (I->getOpcode() != PPC::BCC &&
361       I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
362       I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
363     return 1;
364 
365   // Remove the branch.
366   I->eraseFromParent();
367   return 2;
368 }
369 
370 unsigned
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,const SmallVectorImpl<MachineOperand> & Cond,DebugLoc DL) const371 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
372                            MachineBasicBlock *FBB,
373                            const SmallVectorImpl<MachineOperand> &Cond,
374                            DebugLoc DL) const {
375   // Shouldn't be a fall through.
376   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
377   assert((Cond.size() == 2 || Cond.size() == 0) &&
378          "PPC branch conditions have two components!");
379 
380   bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
381 
382   // One-way branch.
383   if (FBB == 0) {
384     if (Cond.empty())   // Unconditional branch
385       BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
386     else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
387       BuildMI(&MBB, DL, get(Cond[0].getImm() ?
388                               (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
389                               (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
390     else                // Conditional branch
391       BuildMI(&MBB, DL, get(PPC::BCC))
392         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
393     return 1;
394   }
395 
396   // Two-way Conditional Branch.
397   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
398     BuildMI(&MBB, DL, get(Cond[0].getImm() ?
399                             (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
400                             (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
401   else
402     BuildMI(&MBB, DL, get(PPC::BCC))
403       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
404   BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
405   return 2;
406 }
407 
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const408 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
409                                MachineBasicBlock::iterator I, DebugLoc DL,
410                                unsigned DestReg, unsigned SrcReg,
411                                bool KillSrc) const {
412   unsigned Opc;
413   if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
414     Opc = PPC::OR;
415   else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
416     Opc = PPC::OR8;
417   else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
418     Opc = PPC::FMR;
419   else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
420     Opc = PPC::MCRF;
421   else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
422     Opc = PPC::VOR;
423   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
424     Opc = PPC::CROR;
425   else
426     llvm_unreachable("Impossible reg-to-reg copy");
427 
428   const MCInstrDesc &MCID = get(Opc);
429   if (MCID.getNumOperands() == 3)
430     BuildMI(MBB, I, DL, MCID, DestReg)
431       .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
432   else
433     BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
434 }
435 
436 // This function returns true if a CR spill is necessary and false otherwise.
437 bool
StoreRegToStackSlot(MachineFunction & MF,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs,bool & NonRI) const438 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
439                                   unsigned SrcReg, bool isKill,
440                                   int FrameIdx,
441                                   const TargetRegisterClass *RC,
442                                   SmallVectorImpl<MachineInstr*> &NewMIs,
443                                   bool &NonRI) const{
444   DebugLoc DL;
445   if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
446     if (SrcReg != PPC::LR) {
447       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
448                                          .addReg(SrcReg,
449                                                  getKillRegState(isKill)),
450                                          FrameIdx));
451     } else {
452       // FIXME: this spills LR immediately to memory in one step.  To do this,
453       // we use R11, which we know cannot be used in the prolog/epilog.  This is
454       // a hack.
455       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
456       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
457                                          .addReg(PPC::R11,
458                                                  getKillRegState(isKill)),
459                                          FrameIdx));
460     }
461   } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
462     if (SrcReg != PPC::LR8) {
463       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
464                                          .addReg(SrcReg,
465                                                  getKillRegState(isKill)),
466                                          FrameIdx));
467     } else {
468       // FIXME: this spills LR immediately to memory in one step.  To do this,
469       // we use X11, which we know cannot be used in the prolog/epilog.  This is
470       // a hack.
471       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
472       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
473                                          .addReg(PPC::X11,
474                                                  getKillRegState(isKill)),
475                                          FrameIdx));
476     }
477   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
478     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
479                                        .addReg(SrcReg,
480                                                getKillRegState(isKill)),
481                                        FrameIdx));
482   } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
483     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
484                                        .addReg(SrcReg,
485                                                getKillRegState(isKill)),
486                                        FrameIdx));
487   } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
488     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
489                                        .addReg(SrcReg,
490                                                getKillRegState(isKill)),
491                                        FrameIdx));
492     return true;
493   } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
494     // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
495     // backend currently only uses CR1EQ as an individual bit, this should
496     // not cause any bug. If we need other uses of CR bits, the following
497     // code may be invalid.
498     unsigned Reg = 0;
499     if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
500         SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
501       Reg = PPC::CR0;
502     else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
503              SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
504       Reg = PPC::CR1;
505     else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
506              SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
507       Reg = PPC::CR2;
508     else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
509              SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
510       Reg = PPC::CR3;
511     else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
512              SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
513       Reg = PPC::CR4;
514     else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
515              SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
516       Reg = PPC::CR5;
517     else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
518              SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
519       Reg = PPC::CR6;
520     else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
521              SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
522       Reg = PPC::CR7;
523 
524     return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
525                                &PPC::CRRCRegClass, NewMIs, NonRI);
526 
527   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
528     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
529                                        .addReg(SrcReg,
530                                                getKillRegState(isKill)),
531                                        FrameIdx));
532     NonRI = true;
533   } else {
534     llvm_unreachable("Unknown regclass!");
535   }
536 
537   return false;
538 }
539 
540 void
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const541 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
542                                   MachineBasicBlock::iterator MI,
543                                   unsigned SrcReg, bool isKill, int FrameIdx,
544                                   const TargetRegisterClass *RC,
545                                   const TargetRegisterInfo *TRI) const {
546   MachineFunction &MF = *MBB.getParent();
547   SmallVector<MachineInstr*, 4> NewMIs;
548 
549   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
550   FuncInfo->setHasSpills();
551 
552   bool NonRI = false;
553   if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, NonRI))
554     FuncInfo->setSpillsCR();
555 
556   if (NonRI)
557     FuncInfo->setHasNonRISpills();
558 
559   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
560     MBB.insert(MI, NewMIs[i]);
561 
562   const MachineFrameInfo &MFI = *MF.getFrameInfo();
563   MachineMemOperand *MMO =
564     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
565                             MachineMemOperand::MOStore,
566                             MFI.getObjectSize(FrameIdx),
567                             MFI.getObjectAlignment(FrameIdx));
568   NewMIs.back()->addMemOperand(MF, MMO);
569 }
570 
571 bool
LoadRegFromStackSlot(MachineFunction & MF,DebugLoc DL,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs,bool & NonRI) const572 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
573                                    unsigned DestReg, int FrameIdx,
574                                    const TargetRegisterClass *RC,
575                                    SmallVectorImpl<MachineInstr*> &NewMIs,
576                                    bool &NonRI) const{
577   if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
578     if (DestReg != PPC::LR) {
579       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
580                                                  DestReg), FrameIdx));
581     } else {
582       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
583                                                  PPC::R11), FrameIdx));
584       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
585     }
586   } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
587     if (DestReg != PPC::LR8) {
588       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
589                                          FrameIdx));
590     } else {
591       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
592                                                  PPC::X11), FrameIdx));
593       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
594     }
595   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
596     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
597                                        FrameIdx));
598   } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
599     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
600                                        FrameIdx));
601   } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
602     NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
603                                                get(PPC::RESTORE_CR), DestReg),
604                                        FrameIdx));
605     return true;
606   } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
607 
608     unsigned Reg = 0;
609     if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
610         DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
611       Reg = PPC::CR0;
612     else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
613              DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
614       Reg = PPC::CR1;
615     else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
616              DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
617       Reg = PPC::CR2;
618     else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
619              DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
620       Reg = PPC::CR3;
621     else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
622              DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
623       Reg = PPC::CR4;
624     else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
625              DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
626       Reg = PPC::CR5;
627     else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
628              DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
629       Reg = PPC::CR6;
630     else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
631              DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
632       Reg = PPC::CR7;
633 
634     return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
635                                 &PPC::CRRCRegClass, NewMIs, NonRI);
636 
637   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
638     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
639                                        FrameIdx));
640     NonRI = true;
641   } else {
642     llvm_unreachable("Unknown regclass!");
643   }
644 
645   return false;
646 }
647 
648 void
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const649 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
650                                    MachineBasicBlock::iterator MI,
651                                    unsigned DestReg, int FrameIdx,
652                                    const TargetRegisterClass *RC,
653                                    const TargetRegisterInfo *TRI) const {
654   MachineFunction &MF = *MBB.getParent();
655   SmallVector<MachineInstr*, 4> NewMIs;
656   DebugLoc DL;
657   if (MI != MBB.end()) DL = MI->getDebugLoc();
658 
659   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
660   FuncInfo->setHasSpills();
661 
662   bool NonRI = false;
663   if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, NonRI))
664     FuncInfo->setSpillsCR();
665 
666   if (NonRI)
667     FuncInfo->setHasNonRISpills();
668 
669   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
670     MBB.insert(MI, NewMIs[i]);
671 
672   const MachineFrameInfo &MFI = *MF.getFrameInfo();
673   MachineMemOperand *MMO =
674     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
675                             MachineMemOperand::MOLoad,
676                             MFI.getObjectSize(FrameIdx),
677                             MFI.getObjectAlignment(FrameIdx));
678   NewMIs.back()->addMemOperand(MF, MMO);
679 }
680 
681 MachineInstr*
emitFrameIndexDebugValue(MachineFunction & MF,int FrameIx,uint64_t Offset,const MDNode * MDPtr,DebugLoc DL) const682 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
683                                        int FrameIx, uint64_t Offset,
684                                        const MDNode *MDPtr,
685                                        DebugLoc DL) const {
686   MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
687   addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
688   return &*MIB;
689 }
690 
691 bool PPCInstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const692 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
693   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
694   if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
695     Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
696   else
697     // Leave the CR# the same, but invert the condition.
698     Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
699   return false;
700 }
701 
702 /// GetInstSize - Return the number of bytes of code the specified
703 /// instruction may be.  This returns the maximum number of bytes.
704 ///
GetInstSizeInBytes(const MachineInstr * MI) const705 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
706   switch (MI->getOpcode()) {
707   case PPC::INLINEASM: {       // Inline Asm: Variable size.
708     const MachineFunction *MF = MI->getParent()->getParent();
709     const char *AsmStr = MI->getOperand(0).getSymbolName();
710     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
711   }
712   case PPC::PROLOG_LABEL:
713   case PPC::EH_LABEL:
714   case PPC::GC_LABEL:
715   case PPC::DBG_VALUE:
716     return 0;
717   case PPC::BL8_NOP_ELF:
718   case PPC::BLA8_NOP_ELF:
719     return 8;
720   default:
721     return 4; // PowerPC instructions are all 4 bytes
722   }
723 }
724