1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //
23 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "hexagon-nvj"
25 #include "Hexagon.h"
26 #include "HexagonInstrInfo.h"
27 #include "HexagonMachineFunctionInfo.h"
28 #include "HexagonRegisterInfo.h"
29 #include "HexagonSubtarget.h"
30 #include "HexagonTargetMachine.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
40 #include "llvm/PassSupport.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include <map>
48 using namespace llvm;
49
50 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
51
52 static cl::opt<int>
53 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
54 "Maximum number of predicated jumps to be converted to New Value Jump"));
55
56 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
57 cl::ZeroOrMore, cl::init(false),
58 cl::desc("Disable New Value Jumps"));
59
60 namespace {
61 struct HexagonNewValueJump : public MachineFunctionPass {
62 const HexagonInstrInfo *QII;
63 const HexagonRegisterInfo *QRI;
64
65 public:
66 static char ID;
67
HexagonNewValueJump__anond6da2cb40111::HexagonNewValueJump68 HexagonNewValueJump() : MachineFunctionPass(ID) { }
69
getAnalysisUsage__anond6da2cb40111::HexagonNewValueJump70 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
71 MachineFunctionPass::getAnalysisUsage(AU);
72 }
73
getPassName__anond6da2cb40111::HexagonNewValueJump74 const char *getPassName() const {
75 return "Hexagon NewValueJump";
76 }
77
78 virtual bool runOnMachineFunction(MachineFunction &Fn);
79
80 private:
81
82 };
83
84 } // end of anonymous namespace
85
86 char HexagonNewValueJump::ID = 0;
87
88 // We have identified this II could be feeder to NVJ,
89 // verify that it can be.
canBeFeederToNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,MachineBasicBlock::iterator end,MachineBasicBlock::iterator skip,MachineFunction & MF)90 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
91 const TargetRegisterInfo *TRI,
92 MachineBasicBlock::iterator II,
93 MachineBasicBlock::iterator end,
94 MachineBasicBlock::iterator skip,
95 MachineFunction &MF) {
96
97 // Predicated instruction can not be feeder to NVJ.
98 if (QII->isPredicated(II))
99 return false;
100
101 // Bail out if feederReg is a paired register (double regs in
102 // our case). One would think that we can check to see if a given
103 // register cmpReg1 or cmpReg2 is a sub register of feederReg
104 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
105 // before the callsite of this function
106 // But we can not as it comes in the following fashion.
107 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
108 // %R0<def> = KILL %R0, %D0<imp-use,kill>
109 // %P0<def> = CMPEQri %R0<kill>, 0
110 // Hence, we need to check if it's a KILL instruction.
111 if (II->getOpcode() == TargetOpcode::KILL)
112 return false;
113
114
115 // Make sure there there is no 'def' or 'use' of any of the uses of
116 // feeder insn between it's definition, this MI and jump, jmpInst
117 // skipping compare, cmpInst.
118 // Here's the example.
119 // r21=memub(r22+r24<<#0)
120 // p0 = cmp.eq(r21, #0)
121 // r4=memub(r3+r21<<#0)
122 // if (p0.new) jump:t .LBB29_45
123 // Without this check, it will be converted into
124 // r4=memub(r3+r21<<#0)
125 // r21=memub(r22+r24<<#0)
126 // p0 = cmp.eq(r21, #0)
127 // if (p0.new) jump:t .LBB29_45
128 // and result WAR hazards if converted to New Value Jump.
129
130 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
131 if (II->getOperand(i).isReg() &&
132 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
133 MachineBasicBlock::iterator localII = II;
134 ++localII;
135 unsigned Reg = II->getOperand(i).getReg();
136 for (MachineBasicBlock::iterator localBegin = localII;
137 localBegin != end; ++localBegin) {
138 if (localBegin == skip ) continue;
139 // Check for Subregisters too.
140 if (localBegin->modifiesRegister(Reg, TRI) ||
141 localBegin->readsRegister(Reg, TRI))
142 return false;
143 }
144 }
145 }
146 return true;
147 }
148
149 // These are the common checks that need to performed
150 // to determine if
151 // 1. compare instruction can be moved before jump.
152 // 2. feeder to the compare instruction can be moved before jump.
commonChecksToProhibitNewValueJump(bool afterRA,MachineBasicBlock::iterator MII)153 static bool commonChecksToProhibitNewValueJump(bool afterRA,
154 MachineBasicBlock::iterator MII) {
155
156 // If store in path, bail out.
157 if (MII->getDesc().mayStore())
158 return false;
159
160 // if call in path, bail out.
161 if (MII->getOpcode() == Hexagon::CALLv3)
162 return false;
163
164 // if NVJ is running prior to RA, do the following checks.
165 if (!afterRA) {
166 // The following Target Opcode instructions are spurious
167 // to new value jump. If they are in the path, bail out.
168 // KILL sets kill flag on the opcode. It also sets up a
169 // single register, out of pair.
170 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
171 // %R0<def> = KILL %R0, %D0<imp-use,kill>
172 // %P0<def> = CMPEQri %R0<kill>, 0
173 // PHI can be anything after RA.
174 // COPY can remateriaze things in between feeder, compare and nvj.
175 if (MII->getOpcode() == TargetOpcode::KILL ||
176 MII->getOpcode() == TargetOpcode::PHI ||
177 MII->getOpcode() == TargetOpcode::COPY)
178 return false;
179
180 // The following pseudo Hexagon instructions sets "use" and "def"
181 // of registers by individual passes in the backend. At this time,
182 // we don't know the scope of usage and definitions of these
183 // instructions.
184 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
185 MII->getOpcode() == Hexagon::TFR_condset_ii ||
186 MII->getOpcode() == Hexagon::TFR_condset_ri ||
187 MII->getOpcode() == Hexagon::TFR_condset_ir ||
188 MII->getOpcode() == Hexagon::LDriw_pred ||
189 MII->getOpcode() == Hexagon::STriw_pred)
190 return false;
191 }
192
193 return true;
194 }
195
canCompareBeNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,unsigned pReg,bool secondReg,bool optLocation,MachineBasicBlock::iterator end,MachineFunction & MF)196 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
197 const TargetRegisterInfo *TRI,
198 MachineBasicBlock::iterator II,
199 unsigned pReg,
200 bool secondReg,
201 bool optLocation,
202 MachineBasicBlock::iterator end,
203 MachineFunction &MF) {
204
205 MachineInstr *MI = II;
206
207 // If the second operand of the compare is an imm, make sure it's in the
208 // range specified by the arch.
209 if (!secondReg) {
210 int64_t v = MI->getOperand(2).getImm();
211 if (MI->getOpcode() == Hexagon::CMPGEri ||
212 (MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
213 --v;
214
215 if (!(isUInt<5>(v) ||
216 ((MI->getOpcode() == Hexagon::CMPEQri ||
217 MI->getOpcode() == Hexagon::CMPGTri ||
218 MI->getOpcode() == Hexagon::CMPGEri) &&
219 (v == -1))))
220 return false;
221 }
222
223 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
224 cmpReg1 = MI->getOperand(1).getReg();
225
226 if (secondReg) {
227 cmpOp2 = MI->getOperand(2).getReg();
228
229 // Make sure that that second register is not from COPY
230 // At machine code level, we don't need this, but if we decide
231 // to move new value jump prior to RA, we would be needing this.
232 MachineRegisterInfo &MRI = MF.getRegInfo();
233 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
234 MachineInstr *def = MRI.getVRegDef(cmpOp2);
235 if (def->getOpcode() == TargetOpcode::COPY)
236 return false;
237 }
238 }
239
240 // Walk the instructions after the compare (predicate def) to the jump,
241 // and satisfy the following conditions.
242 ++II ;
243 for (MachineBasicBlock::iterator localII = II; localII != end;
244 ++localII) {
245
246 // Check 1.
247 // If "common" checks fail, bail out.
248 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
249 return false;
250
251 // Check 2.
252 // If there is a def or use of predicate (result of compare), bail out.
253 if (localII->modifiesRegister(pReg, TRI) ||
254 localII->readsRegister(pReg, TRI))
255 return false;
256
257 // Check 3.
258 // If there is a def of any of the use of the compare (operands of compare),
259 // bail out.
260 // Eg.
261 // p0 = cmp.eq(r2, r0)
262 // r2 = r4
263 // if (p0.new) jump:t .LBB28_3
264 if (localII->modifiesRegister(cmpReg1, TRI) ||
265 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
266 return false;
267 }
268 return true;
269 }
270
271 // Given a compare operator, return a matching New Value Jump
272 // compare operator. Make sure that MI here is included in
273 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
getNewValueJumpOpcode(const MachineInstr * MI,int reg,bool secondRegNewified)274 static unsigned getNewValueJumpOpcode(const MachineInstr *MI, int reg,
275 bool secondRegNewified) {
276 switch (MI->getOpcode()) {
277 case Hexagon::CMPEQrr:
278 return Hexagon::JMP_EQrrPt_nv_V4;
279
280 case Hexagon::CMPEQri: {
281 if (reg >= 0)
282 return Hexagon::JMP_EQriPt_nv_V4;
283 else
284 return Hexagon::JMP_EQriPtneg_nv_V4;
285 }
286
287 case Hexagon::CMPLTrr:
288 case Hexagon::CMPGTrr: {
289 if (secondRegNewified)
290 return Hexagon::JMP_GTrrdnPt_nv_V4;
291 else
292 return Hexagon::JMP_GTrrPt_nv_V4;
293 }
294
295 case Hexagon::CMPGEri: {
296 if (reg >= 1)
297 return Hexagon::JMP_GTriPt_nv_V4;
298 else
299 return Hexagon::JMP_GTriPtneg_nv_V4;
300 }
301
302 case Hexagon::CMPGTri: {
303 if (reg >= 0)
304 return Hexagon::JMP_GTriPt_nv_V4;
305 else
306 return Hexagon::JMP_GTriPtneg_nv_V4;
307 }
308
309 case Hexagon::CMPLTUrr:
310 case Hexagon::CMPGTUrr: {
311 if (secondRegNewified)
312 return Hexagon::JMP_GTUrrdnPt_nv_V4;
313 else
314 return Hexagon::JMP_GTUrrPt_nv_V4;
315 }
316
317 case Hexagon::CMPGTUri:
318 return Hexagon::JMP_GTUriPt_nv_V4;
319
320 case Hexagon::CMPGEUri: {
321 if (reg == 0)
322 return Hexagon::JMP_EQrrPt_nv_V4;
323 else
324 return Hexagon::JMP_GTUriPt_nv_V4;
325 }
326
327 default:
328 llvm_unreachable("Could not find matching New Value Jump instruction.");
329 }
330 // return *some value* to avoid compiler warning
331 return 0;
332 }
333
runOnMachineFunction(MachineFunction & MF)334 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
335
336 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
337 << "********** Function: "
338 << MF.getName() << "\n");
339
340 #if 0
341 // for now disable this, if we move NewValueJump before register
342 // allocation we need this information.
343 LiveVariables &LVs = getAnalysis<LiveVariables>();
344 #endif
345
346 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
347 QRI =
348 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
349
350 if (!QRI->Subtarget.hasV4TOps() ||
351 DisableNewValueJumps) {
352 return false;
353 }
354
355 int nvjCount = DbgNVJCount;
356 int nvjGenerated = 0;
357
358 // Loop through all the bb's of the function
359 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
360 MBBb != MBBe; ++MBBb) {
361 MachineBasicBlock* MBB = MBBb;
362
363 DEBUG(dbgs() << "** dumping bb ** "
364 << MBB->getNumber() << "\n");
365 DEBUG(MBB->dump());
366 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
367 bool foundJump = false;
368 bool foundCompare = false;
369 bool invertPredicate = false;
370 unsigned predReg = 0; // predicate reg of the jump.
371 unsigned cmpReg1 = 0;
372 int cmpOp2 = 0;
373 bool MO1IsKill = false;
374 bool MO2IsKill = false;
375 MachineBasicBlock::iterator jmpPos;
376 MachineBasicBlock::iterator cmpPos;
377 MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
378 MachineBasicBlock *jmpTarget = NULL;
379 bool afterRA = false;
380 bool isSecondOpReg = false;
381 bool isSecondOpNewified = false;
382 // Traverse the basic block - bottom up
383 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
384 MII != E;) {
385 MachineInstr *MI = --MII;
386 if (MI->isDebugValue()) {
387 continue;
388 }
389
390 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
391 break;
392
393 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
394
395 if (!foundJump &&
396 (MI->getOpcode() == Hexagon::JMP_c ||
397 MI->getOpcode() == Hexagon::JMP_cNot ||
398 MI->getOpcode() == Hexagon::JMP_cdnPt ||
399 MI->getOpcode() == Hexagon::JMP_cdnPnt ||
400 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
401 MI->getOpcode() == Hexagon::JMP_cdnNotPnt)) {
402 // This is where you would insert your compare and
403 // instr that feeds compare
404 jmpPos = MII;
405 jmpInstr = MI;
406 predReg = MI->getOperand(0).getReg();
407 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
408
409 // If ifconverter had not messed up with the kill flags of the
410 // operands, the following check on the kill flag would suffice.
411 // if(!jmpInstr->getOperand(0).isKill()) break;
412
413 // This predicate register is live out out of BB
414 // this would only work if we can actually use Live
415 // variable analysis on phy regs - but LLVM does not
416 // provide LV analysis on phys regs.
417 //if(LVs.isLiveOut(predReg, *MBB)) break;
418
419 // Get all the successors of this block - which will always
420 // be 2. Check if the predicate register is live in in those
421 // successor. If yes, we can not delete the predicate -
422 // I am doing this only because LLVM does not provide LiveOut
423 // at the BB level.
424 bool predLive = false;
425 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
426 SIE = MBB->succ_end(); SI != SIE; ++SI) {
427 MachineBasicBlock* succMBB = *SI;
428 if (succMBB->isLiveIn(predReg)) {
429 predLive = true;
430 }
431 }
432 if (predLive)
433 break;
434
435 jmpTarget = MI->getOperand(1).getMBB();
436 foundJump = true;
437 if (MI->getOpcode() == Hexagon::JMP_cNot ||
438 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
439 MI->getOpcode() == Hexagon::JMP_cdnNotPnt) {
440 invertPredicate = true;
441 }
442 continue;
443 }
444
445 // No new value jump if there is a barrier. A barrier has to be in its
446 // own packet. A barrier has zero operands. We conservatively bail out
447 // here if we see any instruction with zero operands.
448 if (foundJump && MI->getNumOperands() == 0)
449 break;
450
451 if (foundJump &&
452 !foundCompare &&
453 MI->getOperand(0).isReg() &&
454 MI->getOperand(0).getReg() == predReg) {
455
456 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
457 if (QII->isNewValueJumpCandidate(MI)) {
458
459 assert((MI->getDesc().isCompare()) &&
460 "Only compare instruction can be collapsed into New Value Jump");
461 isSecondOpReg = MI->getOperand(2).isReg();
462
463 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
464 afterRA, jmpPos, MF))
465 break;
466
467 cmpInstr = MI;
468 cmpPos = MII;
469 foundCompare = true;
470
471 // We need cmpReg1 and cmpOp2(imm or reg) while building
472 // new value jump instruction.
473 cmpReg1 = MI->getOperand(1).getReg();
474 if (MI->getOperand(1).isKill())
475 MO1IsKill = true;
476
477 if (isSecondOpReg) {
478 cmpOp2 = MI->getOperand(2).getReg();
479 if (MI->getOperand(2).isKill())
480 MO2IsKill = true;
481 } else
482 cmpOp2 = MI->getOperand(2).getImm();
483 continue;
484 }
485 }
486
487 if (foundCompare && foundJump) {
488
489 // If "common" checks fail, bail out on this BB.
490 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
491 break;
492
493 bool foundFeeder = false;
494 MachineBasicBlock::iterator feederPos = MII;
495 if (MI->getOperand(0).isReg() &&
496 MI->getOperand(0).isDef() &&
497 (MI->getOperand(0).getReg() == cmpReg1 ||
498 (isSecondOpReg &&
499 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
500
501 unsigned feederReg = MI->getOperand(0).getReg();
502
503 // First try to see if we can get the feeder from the first operand
504 // of the compare. If we can not, and if secondOpReg is true
505 // (second operand of the compare is also register), try that one.
506 // TODO: Try to come up with some heuristic to figure out which
507 // feeder would benefit.
508
509 if (feederReg == cmpReg1) {
510 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
511 if (!isSecondOpReg)
512 break;
513 else
514 continue;
515 } else
516 foundFeeder = true;
517 }
518
519 if (!foundFeeder &&
520 isSecondOpReg &&
521 feederReg == (unsigned) cmpOp2)
522 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
523 break;
524
525 if (isSecondOpReg) {
526 // In case of CMPLT, or CMPLTU, or EQ with the second register
527 // to newify, swap the operands.
528 if (cmpInstr->getOpcode() == Hexagon::CMPLTrr ||
529 cmpInstr->getOpcode() == Hexagon::CMPLTUrr ||
530 (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
531 feederReg == (unsigned) cmpOp2)) {
532 unsigned tmp = cmpReg1;
533 bool tmpIsKill = MO1IsKill;
534 cmpReg1 = cmpOp2;
535 MO1IsKill = MO2IsKill;
536 cmpOp2 = tmp;
537 MO2IsKill = tmpIsKill;
538 }
539
540 // Now we have swapped the operands, all we need to check is,
541 // if the second operand (after swap) is the feeder.
542 // And if it is, make a note.
543 if (feederReg == (unsigned)cmpOp2)
544 isSecondOpNewified = true;
545 }
546
547 // Now that we are moving feeder close the jump,
548 // make sure we are respecting the kill values of
549 // the operands of the feeder.
550
551 bool updatedIsKill = false;
552 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
553 MachineOperand &MO = MI->getOperand(i);
554 if (MO.isReg() && MO.isUse()) {
555 unsigned feederReg = MO.getReg();
556 for (MachineBasicBlock::iterator localII = feederPos,
557 end = jmpPos; localII != end; localII++) {
558 MachineInstr *localMI = localII;
559 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
560 MachineOperand &localMO = localMI->getOperand(j);
561 if (localMO.isReg() && localMO.isUse() &&
562 localMO.isKill() && feederReg == localMO.getReg()) {
563 // We found that there is kill of a use register
564 // Set up a kill flag on the register
565 localMO.setIsKill(false);
566 MO.setIsKill();
567 updatedIsKill = true;
568 break;
569 }
570 }
571 if (updatedIsKill) break;
572 }
573 }
574 if (updatedIsKill) break;
575 }
576
577 MBB->splice(jmpPos, MI->getParent(), MI);
578 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
579 DebugLoc dl = MI->getDebugLoc();
580 MachineInstr *NewMI;
581
582 assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
583 "This compare is not a New Value Jump candidate.");
584 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
585 isSecondOpNewified);
586 if (invertPredicate)
587 opc = QII->getInvertedPredicatedOpcode(opc);
588
589 // Manage the conversions from CMPGEUri to either CMPEQrr
590 // or CMPGTUri properly. See Arch spec for CMPGEUri instructions.
591 // This has to be after the getNewValueJumpOpcode function call as
592 // second operand of the compare could be modified in this logic.
593 if (cmpInstr->getOpcode() == Hexagon::CMPGEUri) {
594 if (cmpOp2 == 0) {
595 cmpOp2 = cmpReg1;
596 MO2IsKill = MO1IsKill;
597 isSecondOpReg = true;
598 } else
599 --cmpOp2;
600 }
601
602 // Manage the conversions from CMPGEri to CMPGTUri properly.
603 // See Arch spec for CMPGEri instructions.
604 if (cmpInstr->getOpcode() == Hexagon::CMPGEri)
605 --cmpOp2;
606
607 if (isSecondOpReg) {
608 NewMI = BuildMI(*MBB, jmpPos, dl,
609 QII->get(opc))
610 .addReg(cmpReg1, getKillRegState(MO1IsKill))
611 .addReg(cmpOp2, getKillRegState(MO2IsKill))
612 .addMBB(jmpTarget);
613 }
614 else {
615 NewMI = BuildMI(*MBB, jmpPos, dl,
616 QII->get(opc))
617 .addReg(cmpReg1, getKillRegState(MO1IsKill))
618 .addImm(cmpOp2)
619 .addMBB(jmpTarget);
620 }
621
622 assert(NewMI && "New Value Jump Instruction Not created!");
623 if (cmpInstr->getOperand(0).isReg() &&
624 cmpInstr->getOperand(0).isKill())
625 cmpInstr->getOperand(0).setIsKill(false);
626 if (cmpInstr->getOperand(1).isReg() &&
627 cmpInstr->getOperand(1).isKill())
628 cmpInstr->getOperand(1).setIsKill(false);
629 cmpInstr->eraseFromParent();
630 jmpInstr->eraseFromParent();
631 ++nvjGenerated;
632 ++NumNVJGenerated;
633 break;
634 }
635 }
636 }
637 }
638
639 return true;
640
641 }
642
createHexagonNewValueJump()643 FunctionPass *llvm::createHexagonNewValueJump() {
644 return new HexagonNewValueJump();
645 }
646