1 //===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
12 /// group to work correctly. This pass expands these individual instructions
13 /// into several instructions that will completely fill the instruction group.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "AMDGPU.h"
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25
26 using namespace llvm;
27
28 namespace {
29
30 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
31
32 private:
33 static char ID;
34 const R600InstrInfo *TII;
35
36 bool ExpandInputPerspective(MachineInstr& MI);
37 bool ExpandInputConstant(MachineInstr& MI);
38
39 public:
R600ExpandSpecialInstrsPass(TargetMachine & tm)40 R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
41 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
42
43 virtual bool runOnMachineFunction(MachineFunction &MF);
44
getPassName() const45 const char *getPassName() const {
46 return "R600 Expand special instructions pass";
47 }
48 };
49
50 } // End anonymous namespace
51
52 char R600ExpandSpecialInstrsPass::ID = 0;
53
createR600ExpandSpecialInstrsPass(TargetMachine & TM)54 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
55 return new R600ExpandSpecialInstrsPass(TM);
56 }
57
runOnMachineFunction(MachineFunction & MF)58 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
59
60 const R600RegisterInfo &TRI = TII->getRegisterInfo();
61
62 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
63 BB != BB_E; ++BB) {
64 MachineBasicBlock &MBB = *BB;
65 MachineBasicBlock::iterator I = MBB.begin();
66 while (I != MBB.end()) {
67 MachineInstr &MI = *I;
68 I = llvm::next(I);
69
70 switch (MI.getOpcode()) {
71 default: break;
72 // Expand PRED_X to one of the PRED_SET instructions.
73 case AMDGPU::PRED_X: {
74 uint64_t Flags = MI.getOperand(3).getImm();
75 // The native opcode used by PRED_X is stored as an immediate in the
76 // third operand.
77 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
78 MI.getOperand(2).getImm(), // opcode
79 MI.getOperand(0).getReg(), // dst
80 MI.getOperand(1).getReg(), // src0
81 AMDGPU::ZERO); // src1
82 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
83 if (Flags & MO_FLAG_PUSH) {
84 TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
85 } else {
86 TII->setImmOperand(PredSet, R600Operands::UPDATE_PREDICATE, 1);
87 }
88 MI.eraseFromParent();
89 continue;
90 }
91 case AMDGPU::BREAK: {
92 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
93 AMDGPU::PRED_SETE_INT,
94 AMDGPU::PREDICATE_BIT,
95 AMDGPU::ZERO,
96 AMDGPU::ZERO);
97 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
98 TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
99
100 BuildMI(MBB, I, MBB.findDebugLoc(I),
101 TII->get(AMDGPU::PREDICATED_BREAK))
102 .addReg(AMDGPU::PREDICATE_BIT);
103 MI.eraseFromParent();
104 continue;
105 }
106
107 case AMDGPU::INTERP_PAIR_XY: {
108 MachineInstr *BMI;
109 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
110 MI.getOperand(2).getImm());
111
112 for (unsigned Chan = 0; Chan < 4; ++Chan) {
113 unsigned DstReg;
114
115 if (Chan < 2)
116 DstReg = MI.getOperand(Chan).getReg();
117 else
118 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
119
120 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
121 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
122
123 if (Chan > 0) {
124 BMI->bundleWithPred();
125 }
126 if (Chan >= 2)
127 TII->addFlag(BMI, 0, MO_FLAG_MASK);
128 if (Chan != 3)
129 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
130 }
131
132 MI.eraseFromParent();
133 continue;
134 }
135
136 case AMDGPU::INTERP_PAIR_ZW: {
137 MachineInstr *BMI;
138 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
139 MI.getOperand(2).getImm());
140
141 for (unsigned Chan = 0; Chan < 4; ++Chan) {
142 unsigned DstReg;
143
144 if (Chan < 2)
145 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
146 else
147 DstReg = MI.getOperand(Chan-2).getReg();
148
149 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
150 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
151
152 if (Chan > 0) {
153 BMI->bundleWithPred();
154 }
155 if (Chan < 2)
156 TII->addFlag(BMI, 0, MO_FLAG_MASK);
157 if (Chan != 3)
158 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
159 }
160
161 MI.eraseFromParent();
162 continue;
163 }
164
165 case AMDGPU::INTERP_VEC_LOAD: {
166 const R600RegisterInfo &TRI = TII->getRegisterInfo();
167 MachineInstr *BMI;
168 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
169 MI.getOperand(1).getImm());
170 unsigned DstReg = MI.getOperand(0).getReg();
171
172 for (unsigned Chan = 0; Chan < 4; ++Chan) {
173 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
175 if (Chan > 0) {
176 BMI->bundleWithPred();
177 }
178 if (Chan != 3)
179 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
180 }
181
182 MI.eraseFromParent();
183 continue;
184 }
185 }
186
187 bool IsReduction = TII->isReductionOp(MI.getOpcode());
188 bool IsVector = TII->isVector(MI);
189 bool IsCube = TII->isCubeOp(MI.getOpcode());
190 if (!IsReduction && !IsVector && !IsCube) {
191 continue;
192 }
193
194 // Expand the instruction
195 //
196 // Reduction instructions:
197 // T0_X = DP4 T1_XYZW, T2_XYZW
198 // becomes:
199 // TO_X = DP4 T1_X, T2_X
200 // TO_Y (write masked) = DP4 T1_Y, T2_Y
201 // TO_Z (write masked) = DP4 T1_Z, T2_Z
202 // TO_W (write masked) = DP4 T1_W, T2_W
203 //
204 // Vector instructions:
205 // T0_X = MULLO_INT T1_X, T2_X
206 // becomes:
207 // T0_X = MULLO_INT T1_X, T2_X
208 // T0_Y (write masked) = MULLO_INT T1_X, T2_X
209 // T0_Z (write masked) = MULLO_INT T1_X, T2_X
210 // T0_W (write masked) = MULLO_INT T1_X, T2_X
211 //
212 // Cube instructions:
213 // T0_XYZW = CUBE T1_XYZW
214 // becomes:
215 // TO_X = CUBE T1_Z, T1_Y
216 // T0_Y = CUBE T1_Z, T1_X
217 // T0_Z = CUBE T1_X, T1_Z
218 // T0_W = CUBE T1_Y, T1_Z
219 for (unsigned Chan = 0; Chan < 4; Chan++) {
220 unsigned DstReg = MI.getOperand(
221 TII->getOperandIdx(MI, R600Operands::DST)).getReg();
222 unsigned Src0 = MI.getOperand(
223 TII->getOperandIdx(MI, R600Operands::SRC0)).getReg();
224 unsigned Src1 = 0;
225
226 // Determine the correct source registers
227 if (!IsCube) {
228 int Src1Idx = TII->getOperandIdx(MI, R600Operands::SRC1);
229 if (Src1Idx != -1) {
230 Src1 = MI.getOperand(Src1Idx).getReg();
231 }
232 }
233 if (IsReduction) {
234 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
235 Src0 = TRI.getSubReg(Src0, SubRegIndex);
236 Src1 = TRI.getSubReg(Src1, SubRegIndex);
237 } else if (IsCube) {
238 static const int CubeSrcSwz[] = {2, 2, 0, 1};
239 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
240 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
241 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
242 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
243 }
244
245 // Determine the correct destination registers;
246 bool Mask = false;
247 bool NotLast = true;
248 if (IsCube) {
249 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
250 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
251 } else {
252 // Mask the write if the original instruction does not write to
253 // the current Channel.
254 Mask = (Chan != TRI.getHWRegChan(DstReg));
255 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
256 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
257 }
258
259 // Set the IsLast bit
260 NotLast = (Chan != 3 );
261
262 // Add the new instruction
263 unsigned Opcode = MI.getOpcode();
264 switch (Opcode) {
265 case AMDGPU::CUBE_r600_pseudo:
266 Opcode = AMDGPU::CUBE_r600_real;
267 break;
268 case AMDGPU::CUBE_eg_pseudo:
269 Opcode = AMDGPU::CUBE_eg_real;
270 break;
271 case AMDGPU::DOT4_r600_pseudo:
272 Opcode = AMDGPU::DOT4_r600_real;
273 break;
274 case AMDGPU::DOT4_eg_pseudo:
275 Opcode = AMDGPU::DOT4_eg_real;
276 break;
277 default:
278 break;
279 }
280
281 MachineInstr *NewMI =
282 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
283
284 if (Chan != 0)
285 NewMI->bundleWithPred();
286 if (Mask) {
287 TII->addFlag(NewMI, 0, MO_FLAG_MASK);
288 }
289 if (NotLast) {
290 TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);
291 }
292 }
293 MI.eraseFromParent();
294 }
295 }
296 return false;
297 }
298