1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
13 ///
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
22 ///
23 /// For example:
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
29 /// SI_END_CF %SGPR0
30 ///
31 /// becomes:
32 ///
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
38 /// // EXEC are zero.
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
40 ///
41 /// label0:
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
47 /// label1:
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
50
51 #include "AMDGPU.h"
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
58
59 using namespace llvm;
60
61 namespace {
62
63 class SILowerControlFlowPass : public MachineFunctionPass {
64
65 private:
66 static const unsigned SkipThreshold = 12;
67
68 static char ID;
69 const TargetRegisterInfo *TRI;
70 const TargetInstrInfo *TII;
71
72 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
73
74 void Skip(MachineInstr &From, MachineOperand &To);
75 void SkipIfDead(MachineInstr &MI);
76
77 void If(MachineInstr &MI);
78 void Else(MachineInstr &MI);
79 void Break(MachineInstr &MI);
80 void IfBreak(MachineInstr &MI);
81 void ElseBreak(MachineInstr &MI);
82 void Loop(MachineInstr &MI);
83 void EndCf(MachineInstr &MI);
84
85 void Kill(MachineInstr &MI);
86 void Branch(MachineInstr &MI);
87
88 void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
89 void IndirectSrc(MachineInstr &MI);
90 void IndirectDst(MachineInstr &MI);
91
92 public:
SILowerControlFlowPass(TargetMachine & tm)93 SILowerControlFlowPass(TargetMachine &tm) :
94 MachineFunctionPass(ID), TRI(tm.getRegisterInfo()),
95 TII(tm.getInstrInfo()) { }
96
97 virtual bool runOnMachineFunction(MachineFunction &MF);
98
getPassName() const99 const char *getPassName() const {
100 return "SI Lower control flow instructions";
101 }
102
103 };
104
105 } // End anonymous namespace
106
107 char SILowerControlFlowPass::ID = 0;
108
createSILowerControlFlowPass(TargetMachine & tm)109 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
110 return new SILowerControlFlowPass(tm);
111 }
112
shouldSkip(MachineBasicBlock * From,MachineBasicBlock * To)113 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
114 MachineBasicBlock *To) {
115
116 unsigned NumInstr = 0;
117
118 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
119 MBB = *MBB->succ_begin()) {
120
121 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
122 NumInstr < SkipThreshold && I != E; ++I) {
123
124 if (I->isBundle() || !I->isBundled())
125 if (++NumInstr >= SkipThreshold)
126 return true;
127 }
128 }
129
130 return false;
131 }
132
Skip(MachineInstr & From,MachineOperand & To)133 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
134
135 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
136 return;
137
138 DebugLoc DL = From.getDebugLoc();
139 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
140 .addOperand(To)
141 .addReg(AMDGPU::EXEC);
142 }
143
SkipIfDead(MachineInstr & MI)144 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
145
146 MachineBasicBlock &MBB = *MI.getParent();
147 DebugLoc DL = MI.getDebugLoc();
148
149 if (!shouldSkip(&MBB, &MBB.getParent()->back()))
150 return;
151
152 MachineBasicBlock::iterator Insert = &MI;
153 ++Insert;
154
155 // If the exec mask is non-zero, skip the next two instructions
156 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
157 .addImm(3)
158 .addReg(AMDGPU::EXEC);
159
160 // Exec mask is zero: Export to NULL target...
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
162 .addImm(0)
163 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
164 .addImm(0)
165 .addImm(1)
166 .addImm(1)
167 .addReg(AMDGPU::VGPR0)
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0)
170 .addReg(AMDGPU::VGPR0);
171
172 // ... and terminate wavefront
173 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
174 }
175
If(MachineInstr & MI)176 void SILowerControlFlowPass::If(MachineInstr &MI) {
177 MachineBasicBlock &MBB = *MI.getParent();
178 DebugLoc DL = MI.getDebugLoc();
179 unsigned Reg = MI.getOperand(0).getReg();
180 unsigned Vcc = MI.getOperand(1).getReg();
181
182 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
183 .addReg(Vcc);
184
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
186 .addReg(AMDGPU::EXEC)
187 .addReg(Reg);
188
189 Skip(MI, MI.getOperand(2));
190
191 MI.eraseFromParent();
192 }
193
Else(MachineInstr & MI)194 void SILowerControlFlowPass::Else(MachineInstr &MI) {
195 MachineBasicBlock &MBB = *MI.getParent();
196 DebugLoc DL = MI.getDebugLoc();
197 unsigned Dst = MI.getOperand(0).getReg();
198 unsigned Src = MI.getOperand(1).getReg();
199
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
201 .addReg(Src); // Saved EXEC
202
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
204 .addReg(AMDGPU::EXEC)
205 .addReg(Dst);
206
207 Skip(MI, MI.getOperand(2));
208
209 MI.eraseFromParent();
210 }
211
Break(MachineInstr & MI)212 void SILowerControlFlowPass::Break(MachineInstr &MI) {
213 MachineBasicBlock &MBB = *MI.getParent();
214 DebugLoc DL = MI.getDebugLoc();
215
216 unsigned Dst = MI.getOperand(0).getReg();
217 unsigned Src = MI.getOperand(1).getReg();
218
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
220 .addReg(AMDGPU::EXEC)
221 .addReg(Src);
222
223 MI.eraseFromParent();
224 }
225
IfBreak(MachineInstr & MI)226 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
227 MachineBasicBlock &MBB = *MI.getParent();
228 DebugLoc DL = MI.getDebugLoc();
229
230 unsigned Dst = MI.getOperand(0).getReg();
231 unsigned Vcc = MI.getOperand(1).getReg();
232 unsigned Src = MI.getOperand(2).getReg();
233
234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
235 .addReg(Vcc)
236 .addReg(Src);
237
238 MI.eraseFromParent();
239 }
240
ElseBreak(MachineInstr & MI)241 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
242 MachineBasicBlock &MBB = *MI.getParent();
243 DebugLoc DL = MI.getDebugLoc();
244
245 unsigned Dst = MI.getOperand(0).getReg();
246 unsigned Saved = MI.getOperand(1).getReg();
247 unsigned Src = MI.getOperand(2).getReg();
248
249 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
250 .addReg(Saved)
251 .addReg(Src);
252
253 MI.eraseFromParent();
254 }
255
Loop(MachineInstr & MI)256 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
257 MachineBasicBlock &MBB = *MI.getParent();
258 DebugLoc DL = MI.getDebugLoc();
259 unsigned Src = MI.getOperand(0).getReg();
260
261 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
262 .addReg(AMDGPU::EXEC)
263 .addReg(Src);
264
265 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
266 .addOperand(MI.getOperand(1))
267 .addReg(AMDGPU::EXEC);
268
269 MI.eraseFromParent();
270 }
271
EndCf(MachineInstr & MI)272 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
273 MachineBasicBlock &MBB = *MI.getParent();
274 DebugLoc DL = MI.getDebugLoc();
275 unsigned Reg = MI.getOperand(0).getReg();
276
277 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
278 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
279 .addReg(AMDGPU::EXEC)
280 .addReg(Reg);
281
282 MI.eraseFromParent();
283 }
284
Branch(MachineInstr & MI)285 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
286 MachineBasicBlock *Next = MI.getParent()->getNextNode();
287 MachineBasicBlock *Target = MI.getOperand(0).getMBB();
288 if (Target == Next)
289 MI.eraseFromParent();
290 else
291 assert(0);
292 }
293
Kill(MachineInstr & MI)294 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
295
296 MachineBasicBlock &MBB = *MI.getParent();
297 DebugLoc DL = MI.getDebugLoc();
298
299 // Kill is only allowed in pixel shaders
300 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
301 ShaderType::PIXEL);
302
303 // Clear this pixel from the exec mask if the operand is negative
304 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
305 .addImm(0)
306 .addOperand(MI.getOperand(0));
307
308 MI.eraseFromParent();
309 }
310
LoadM0(MachineInstr & MI,MachineInstr * MovRel)311 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
312
313 MachineBasicBlock &MBB = *MI.getParent();
314 DebugLoc DL = MI.getDebugLoc();
315 MachineBasicBlock::iterator I = MI;
316
317 unsigned Save = MI.getOperand(1).getReg();
318 unsigned Idx = MI.getOperand(3).getReg();
319
320 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
321 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
322 .addReg(Idx);
323 MBB.insert(I, MovRel);
324 MI.eraseFromParent();
325 return;
326 }
327
328 assert(AMDGPU::SReg_64RegClass.contains(Save));
329 assert(AMDGPU::VReg_32RegClass.contains(Idx));
330
331 // Save the EXEC mask
332 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
333 .addReg(AMDGPU::EXEC);
334
335 // Read the next variant into VCC (lower 32 bits) <- also loop target
336 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
337 .addReg(Idx);
338
339 // Move index from VCC into M0
340 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
341 .addReg(AMDGPU::VCC);
342
343 // Compare the just read M0 value to all possible Idx values
344 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
345 .addReg(AMDGPU::M0)
346 .addReg(Idx);
347
348 // Update EXEC, save the original EXEC value to VCC
349 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
350 .addReg(AMDGPU::VCC);
351
352 // Do the actual move
353 MBB.insert(I, MovRel);
354
355 // Update EXEC, switch all done bits to 0 and all todo bits to 1
356 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
357 .addReg(AMDGPU::EXEC)
358 .addReg(AMDGPU::VCC);
359
360 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
362 .addImm(-7)
363 .addReg(AMDGPU::EXEC);
364
365 // Restore EXEC
366 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
367 .addReg(Save);
368
369 MI.eraseFromParent();
370 }
371
IndirectSrc(MachineInstr & MI)372 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
373
374 MachineBasicBlock &MBB = *MI.getParent();
375 DebugLoc DL = MI.getDebugLoc();
376
377 unsigned Dst = MI.getOperand(0).getReg();
378 unsigned Vec = MI.getOperand(2).getReg();
379 unsigned Off = MI.getOperand(4).getImm();
380
381 MachineInstr *MovRel =
382 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
383 .addReg(TRI->getSubReg(Vec, AMDGPU::sub0) + Off)
384 .addReg(AMDGPU::M0, RegState::Implicit)
385 .addReg(Vec, RegState::Implicit);
386
387 LoadM0(MI, MovRel);
388 }
389
IndirectDst(MachineInstr & MI)390 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
391
392 MachineBasicBlock &MBB = *MI.getParent();
393 DebugLoc DL = MI.getDebugLoc();
394
395 unsigned Dst = MI.getOperand(0).getReg();
396 unsigned Off = MI.getOperand(4).getImm();
397 unsigned Val = MI.getOperand(5).getReg();
398
399 MachineInstr *MovRel =
400 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
402 .addReg(Val)
403 .addReg(AMDGPU::M0, RegState::Implicit)
404 .addReg(Dst, RegState::Implicit);
405
406 LoadM0(MI, MovRel);
407 }
408
runOnMachineFunction(MachineFunction & MF)409 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
410
411 bool HaveKill = false;
412 unsigned Depth = 0;
413
414 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
415 BI != BE; ++BI) {
416
417 MachineBasicBlock &MBB = *BI;
418 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
419 I != MBB.end(); I = Next) {
420
421 Next = llvm::next(I);
422 MachineInstr &MI = *I;
423 switch (MI.getOpcode()) {
424 default: break;
425 case AMDGPU::SI_IF:
426 ++Depth;
427 If(MI);
428 break;
429
430 case AMDGPU::SI_ELSE:
431 Else(MI);
432 break;
433
434 case AMDGPU::SI_BREAK:
435 Break(MI);
436 break;
437
438 case AMDGPU::SI_IF_BREAK:
439 IfBreak(MI);
440 break;
441
442 case AMDGPU::SI_ELSE_BREAK:
443 ElseBreak(MI);
444 break;
445
446 case AMDGPU::SI_LOOP:
447 ++Depth;
448 Loop(MI);
449 break;
450
451 case AMDGPU::SI_END_CF:
452 if (--Depth == 0 && HaveKill) {
453 SkipIfDead(MI);
454 HaveKill = false;
455 }
456 EndCf(MI);
457 break;
458
459 case AMDGPU::SI_KILL:
460 if (Depth == 0)
461 SkipIfDead(MI);
462 else
463 HaveKill = true;
464 Kill(MI);
465 break;
466
467 case AMDGPU::S_BRANCH:
468 Branch(MI);
469 break;
470
471 case AMDGPU::SI_INDIRECT_SRC:
472 IndirectSrc(MI);
473 break;
474
475 case AMDGPU::SI_INDIRECT_DST_V2:
476 case AMDGPU::SI_INDIRECT_DST_V4:
477 case AMDGPU::SI_INDIRECT_DST_V8:
478 case AMDGPU::SI_INDIRECT_DST_V16:
479 IndirectDst(MI);
480 break;
481 }
482 }
483 }
484
485 return true;
486 }
487