1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22
23 #define GET_SUBTARGETINFO_TARGET_DESC
24 #define GET_SUBTARGETINFO_CTOR
25 #include "ARMGenSubtargetInfo.inc"
26
27 using namespace llvm;
28
29 cl::opt<bool>
30 ReserveR9("arm-reserve-r9", cl::Hidden,
31 cl::desc("Reserve R9, making it unavailable as GPR"));
32
33 static cl::opt<bool>
34 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
35
36 static cl::opt<bool>
37 UseFusedMulOps("arm-use-mulops",
38 cl::init(true), cl::Hidden);
39
40 static cl::opt<bool>
41 StrictAlign("arm-strict-align", cl::Hidden,
42 cl::desc("Disallow all unaligned memory accesses"));
43
ARMSubtarget(const std::string & TT,const std::string & CPU,const std::string & FS)44 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
45 const std::string &FS)
46 : ARMGenSubtargetInfo(TT, CPU, FS)
47 , ARMProcFamily(Others)
48 , stackAlignment(4)
49 , CPUString(CPU)
50 , TargetTriple(TT)
51 , TargetABI(ARM_ABI_APCS) {
52 initializeEnvironment();
53 resetSubtargetFeatures(CPU, FS);
54 }
55
initializeEnvironment()56 void ARMSubtarget::initializeEnvironment() {
57 HasV4TOps = false;
58 HasV5TOps = false;
59 HasV5TEOps = false;
60 HasV6Ops = false;
61 HasV6T2Ops = false;
62 HasV7Ops = false;
63 HasVFPv2 = false;
64 HasVFPv3 = false;
65 HasVFPv4 = false;
66 HasNEON = false;
67 UseNEONForSinglePrecisionFP = false;
68 UseMulOps = UseFusedMulOps;
69 SlowFPVMLx = false;
70 HasVMLxForwarding = false;
71 SlowFPBrcc = false;
72 InThumbMode = false;
73 HasThumb2 = false;
74 IsMClass = false;
75 NoARM = false;
76 PostRAScheduler = false;
77 IsR9Reserved = ReserveR9;
78 UseMovt = false;
79 SupportsTailCall = false;
80 HasFP16 = false;
81 HasD16 = false;
82 HasHardwareDivide = false;
83 HasHardwareDivideInARM = false;
84 HasT2ExtractPack = false;
85 HasDataBarrier = false;
86 Pref32BitThumb = false;
87 AvoidCPSRPartialUpdate = false;
88 AvoidMOVsShifterOperand = false;
89 HasRAS = false;
90 HasMPExtension = false;
91 FPOnlySP = false;
92 AllowsUnalignedMem = false;
93 Thumb2DSP = false;
94 UseNaClTrap = false;
95 }
96
resetSubtargetFeatures(const MachineFunction * MF)97 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
98 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
99 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
100 "target-cpu");
101 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
102 "target-features");
103 std::string CPU =
104 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
105 std::string FS =
106 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
107 if (!FS.empty()) {
108 initializeEnvironment();
109 resetSubtargetFeatures(CPU, FS);
110 }
111 }
112
resetSubtargetFeatures(StringRef CPU,StringRef FS)113 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
114 if (CPUString.empty())
115 CPUString = "generic";
116
117 // Insert the architecture feature derived from the target triple into the
118 // feature string. This is important for setting features that are implied
119 // based on the architecture version.
120 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
121 CPUString);
122 if (!FS.empty()) {
123 if (!ArchFS.empty())
124 ArchFS = ArchFS + "," + FS.str();
125 else
126 ArchFS = FS;
127 }
128 ParseSubtargetFeatures(CPUString, ArchFS);
129
130 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
131 // ARM version or CPU and then remove this.
132 if (!HasV6T2Ops && hasThumb2())
133 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
134
135 // Keep a pointer to static instruction cost data for the specified CPU.
136 SchedModel = getSchedModelForCPU(CPUString);
137
138 // Initialize scheduling itinerary for the specified CPU.
139 InstrItins = getInstrItineraryForCPU(CPUString);
140
141 if ((TargetTriple.getTriple().find("eabi") != std::string::npos) ||
142 (isTargetIOS() && isMClass()))
143 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
144 // Darwin-EABI conforms to AACPS but not the rest of EABI.
145 TargetABI = ARM_ABI_AAPCS;
146
147 if (isAAPCS_ABI())
148 stackAlignment = 8;
149
150 if (!isTargetIOS())
151 UseMovt = hasV6T2Ops();
152 else {
153 IsR9Reserved = ReserveR9 | !HasV6Ops;
154 UseMovt = DarwinUseMOVT && hasV6T2Ops();
155 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
156 }
157
158 if (!isThumb() || hasThumb2())
159 PostRAScheduler = true;
160
161 // v6+ may or may not support unaligned mem access depending on the system
162 // configuration.
163 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
164 AllowsUnalignedMem = true;
165 }
166
167 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
168 bool
GVIsIndirectSymbol(const GlobalValue * GV,Reloc::Model RelocM) const169 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
170 Reloc::Model RelocM) const {
171 if (RelocM == Reloc::Static)
172 return false;
173
174 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
175 // load from stub.
176 bool isDecl = GV->hasAvailableExternallyLinkage();
177 if (GV->isDeclaration() && !GV->isMaterializable())
178 isDecl = true;
179
180 if (!isTargetDarwin()) {
181 // Extra load is needed for all externally visible.
182 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
183 return false;
184 return true;
185 } else {
186 if (RelocM == Reloc::PIC_) {
187 // If this is a strong reference to a definition, it is definitely not
188 // through a stub.
189 if (!isDecl && !GV->isWeakForLinker())
190 return false;
191
192 // Unless we have a symbol with hidden visibility, we have to go through a
193 // normal $non_lazy_ptr stub because this symbol might be resolved late.
194 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
195 return true;
196
197 // If symbol visibility is hidden, we have a stub for common symbol
198 // references and external declarations.
199 if (isDecl || GV->hasCommonLinkage())
200 // Hidden $non_lazy_ptr reference.
201 return true;
202
203 return false;
204 } else {
205 // If this is a strong reference to a definition, it is definitely not
206 // through a stub.
207 if (!isDecl && !GV->isWeakForLinker())
208 return false;
209
210 // Unless we have a symbol with hidden visibility, we have to go through a
211 // normal $non_lazy_ptr stub because this symbol might be resolved late.
212 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
213 return true;
214 }
215 }
216
217 return false;
218 }
219
getMispredictionPenalty() const220 unsigned ARMSubtarget::getMispredictionPenalty() const {
221 return SchedModel->MispredictPenalty;
222 }
223
enablePostRAScheduler(CodeGenOpt::Level OptLevel,TargetSubtargetInfo::AntiDepBreakMode & Mode,RegClassVector & CriticalPathRCs) const224 bool ARMSubtarget::enablePostRAScheduler(
225 CodeGenOpt::Level OptLevel,
226 TargetSubtargetInfo::AntiDepBreakMode& Mode,
227 RegClassVector& CriticalPathRCs) const {
228 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
229 CriticalPathRCs.clear();
230 CriticalPathRCs.push_back(&ARM::GPRRegClass);
231 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
232 }
233