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1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveInterval analysis pass.  Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
22 
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/IndexedMap.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/CodeGen/LiveInterval.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/SlotIndexes.h"
31 #include "llvm/Support/Allocator.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include <cmath>
34 #include <iterator>
35 
36 namespace llvm {
37 
38   class AliasAnalysis;
39   class LiveRangeCalc;
40   class LiveVariables;
41   class MachineDominatorTree;
42   class MachineLoopInfo;
43   class TargetRegisterInfo;
44   class MachineRegisterInfo;
45   class TargetInstrInfo;
46   class TargetRegisterClass;
47   class VirtRegMap;
48 
49   class LiveIntervals : public MachineFunctionPass {
50     MachineFunction* MF;
51     MachineRegisterInfo* MRI;
52     const TargetMachine* TM;
53     const TargetRegisterInfo* TRI;
54     const TargetInstrInfo* TII;
55     AliasAnalysis *AA;
56     SlotIndexes* Indexes;
57     MachineDominatorTree *DomTree;
58     LiveRangeCalc *LRCalc;
59 
60     /// Special pool allocator for VNInfo's (LiveInterval val#).
61     ///
62     VNInfo::Allocator VNInfoAllocator;
63 
64     /// Live interval pointers for all the virtual registers.
65     IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
66 
67     /// RegMaskSlots - Sorted list of instructions with register mask operands.
68     /// Always use the 'r' slot, RegMasks are normal clobbers, not early
69     /// clobbers.
70     SmallVector<SlotIndex, 8> RegMaskSlots;
71 
72     /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
73     /// pointer to the corresponding register mask.  This pointer can be
74     /// recomputed as:
75     ///
76     ///   MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
77     ///   unsigned OpNum = findRegMaskOperand(MI);
78     ///   RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
79     ///
80     /// This is kept in a separate vector partly because some standard
81     /// libraries don't support lower_bound() with mixed objects, partly to
82     /// improve locality when searching in RegMaskSlots.
83     /// Also see the comment in LiveInterval::find().
84     SmallVector<const uint32_t*, 8> RegMaskBits;
85 
86     /// For each basic block number, keep (begin, size) pairs indexing into the
87     /// RegMaskSlots and RegMaskBits arrays.
88     /// Note that basic block numbers may not be layout contiguous, that's why
89     /// we can't just keep track of the first register mask in each basic
90     /// block.
91     SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
92 
93     /// RegUnitIntervals - Keep a live interval for each register unit as a way
94     /// of tracking fixed physreg interference.
95     SmallVector<LiveInterval*, 0> RegUnitIntervals;
96 
97   public:
98     static char ID; // Pass identification, replacement for typeid
99     LiveIntervals();
100     virtual ~LiveIntervals();
101 
102     // Calculate the spill weight to assign to a single instruction.
103     static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
104 
getInterval(unsigned Reg)105     LiveInterval &getInterval(unsigned Reg) {
106       LiveInterval *LI = VirtRegIntervals[Reg];
107       assert(LI && "Interval does not exist for virtual register");
108       return *LI;
109     }
110 
getInterval(unsigned Reg)111     const LiveInterval &getInterval(unsigned Reg) const {
112       return const_cast<LiveIntervals*>(this)->getInterval(Reg);
113     }
114 
hasInterval(unsigned Reg)115     bool hasInterval(unsigned Reg) const {
116       return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
117     }
118 
119     // Interval creation.
getOrCreateInterval(unsigned Reg)120     LiveInterval &getOrCreateInterval(unsigned Reg) {
121       if (!hasInterval(Reg)) {
122         VirtRegIntervals.grow(Reg);
123         VirtRegIntervals[Reg] = createInterval(Reg);
124       }
125       return getInterval(Reg);
126     }
127 
128     // Interval removal.
removeInterval(unsigned Reg)129     void removeInterval(unsigned Reg) {
130       delete VirtRegIntervals[Reg];
131       VirtRegIntervals[Reg] = 0;
132     }
133 
134     /// addLiveRangeToEndOfBlock - Given a register and an instruction,
135     /// adds a live range from that instruction to the end of its MBB.
136     LiveRange addLiveRangeToEndOfBlock(unsigned reg,
137                                        MachineInstr* startInst);
138 
139     /// shrinkToUses - After removing some uses of a register, shrink its live
140     /// range to just the remaining uses. This method does not compute reaching
141     /// defs for new uses, and it doesn't remove dead defs.
142     /// Dead PHIDef values are marked as unused.
143     /// New dead machine instructions are added to the dead vector.
144     /// Return true if the interval may have been separated into multiple
145     /// connected components.
146     bool shrinkToUses(LiveInterval *li,
147                       SmallVectorImpl<MachineInstr*> *dead = 0);
148 
149     /// extendToIndices - Extend the live range of LI to reach all points in
150     /// Indices. The points in the Indices array must be jointly dominated by
151     /// existing defs in LI. PHI-defs are added as needed to maintain SSA form.
152     ///
153     /// If a SlotIndex in Indices is the end index of a basic block, LI will be
154     /// extended to be live out of the basic block.
155     ///
156     /// See also LiveRangeCalc::extend().
157     void extendToIndices(LiveInterval *LI, ArrayRef<SlotIndex> Indices);
158 
159     /// pruneValue - If an LI value is live at Kill, prune its live range by
160     /// removing any liveness reachable from Kill. Add live range end points to
161     /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
162     /// value's live range.
163     ///
164     /// Calling pruneValue() and extendToIndices() can be used to reconstruct
165     /// SSA form after adding defs to a virtual register.
166     void pruneValue(LiveInterval *LI, SlotIndex Kill,
167                     SmallVectorImpl<SlotIndex> *EndPoints);
168 
getSlotIndexes()169     SlotIndexes *getSlotIndexes() const {
170       return Indexes;
171     }
172 
getAliasAnalysis()173     AliasAnalysis *getAliasAnalysis() const {
174       return AA;
175     }
176 
177     /// isNotInMIMap - returns true if the specified machine instr has been
178     /// removed or was never entered in the map.
isNotInMIMap(const MachineInstr * Instr)179     bool isNotInMIMap(const MachineInstr* Instr) const {
180       return !Indexes->hasIndex(Instr);
181     }
182 
183     /// Returns the base index of the given instruction.
getInstructionIndex(const MachineInstr * instr)184     SlotIndex getInstructionIndex(const MachineInstr *instr) const {
185       return Indexes->getInstructionIndex(instr);
186     }
187 
188     /// Returns the instruction associated with the given index.
getInstructionFromIndex(SlotIndex index)189     MachineInstr* getInstructionFromIndex(SlotIndex index) const {
190       return Indexes->getInstructionFromIndex(index);
191     }
192 
193     /// Return the first index in the given basic block.
getMBBStartIdx(const MachineBasicBlock * mbb)194     SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
195       return Indexes->getMBBStartIdx(mbb);
196     }
197 
198     /// Return the last index in the given basic block.
getMBBEndIdx(const MachineBasicBlock * mbb)199     SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
200       return Indexes->getMBBEndIdx(mbb);
201     }
202 
isLiveInToMBB(const LiveInterval & li,const MachineBasicBlock * mbb)203     bool isLiveInToMBB(const LiveInterval &li,
204                        const MachineBasicBlock *mbb) const {
205       return li.liveAt(getMBBStartIdx(mbb));
206     }
207 
isLiveOutOfMBB(const LiveInterval & li,const MachineBasicBlock * mbb)208     bool isLiveOutOfMBB(const LiveInterval &li,
209                         const MachineBasicBlock *mbb) const {
210       return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
211     }
212 
getMBBFromIndex(SlotIndex index)213     MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
214       return Indexes->getMBBFromIndex(index);
215     }
216 
insertMBBInMaps(MachineBasicBlock * MBB)217     void insertMBBInMaps(MachineBasicBlock *MBB) {
218       Indexes->insertMBBInMaps(MBB);
219       assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
220              "Blocks must be added in order.");
221       RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
222     }
223 
InsertMachineInstrInMaps(MachineInstr * MI)224     SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
225       return Indexes->insertMachineInstrInMaps(MI);
226     }
227 
RemoveMachineInstrFromMaps(MachineInstr * MI)228     void RemoveMachineInstrFromMaps(MachineInstr *MI) {
229       Indexes->removeMachineInstrFromMaps(MI);
230     }
231 
ReplaceMachineInstrInMaps(MachineInstr * MI,MachineInstr * NewMI)232     void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
233       Indexes->replaceMachineInstrInMaps(MI, NewMI);
234     }
235 
findLiveInMBBs(SlotIndex Start,SlotIndex End,SmallVectorImpl<MachineBasicBlock * > & MBBs)236     bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
237                         SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
238       return Indexes->findLiveInMBBs(Start, End, MBBs);
239     }
240 
getVNInfoAllocator()241     VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
242 
243     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
244     virtual void releaseMemory();
245 
246     /// runOnMachineFunction - pass entry point
247     virtual bool runOnMachineFunction(MachineFunction&);
248 
249     /// print - Implement the dump method.
250     virtual void print(raw_ostream &O, const Module* = 0) const;
251 
252     /// intervalIsInOneMBB - If LI is confined to a single basic block, return
253     /// a pointer to that block.  If LI is live in to or out of any block,
254     /// return NULL.
255     MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
256 
257     /// Returns true if VNI is killed by any PHI-def values in LI.
258     /// This may conservatively return true to avoid expensive computations.
259     bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
260 
261     /// addKillFlags - Add kill flags to any instruction that kills a virtual
262     /// register.
263     void addKillFlags(const VirtRegMap*);
264 
265     /// handleMove - call this method to notify LiveIntervals that
266     /// instruction 'mi' has been moved within a basic block. This will update
267     /// the live intervals for all operands of mi. Moves between basic blocks
268     /// are not supported.
269     ///
270     /// \param UpdateFlags Update live intervals for nonallocatable physregs.
271     void handleMove(MachineInstr* MI, bool UpdateFlags = false);
272 
273     /// moveIntoBundle - Update intervals for operands of MI so that they
274     /// begin/end on the SlotIndex for BundleStart.
275     ///
276     /// \param UpdateFlags Update live intervals for nonallocatable physregs.
277     ///
278     /// Requires MI and BundleStart to have SlotIndexes, and assumes
279     /// existing liveness is accurate. BundleStart should be the first
280     /// instruction in the Bundle.
281     void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
282                               bool UpdateFlags = false);
283 
284     /// repairIntervalsInRange - Update live intervals for instructions in a
285     /// range of iterators. It is intended for use after target hooks that may
286     /// insert or remove instructions, and is only efficient for a small number
287     /// of instructions.
288     ///
289     /// OrigRegs is a vector of registers that were originally used by the
290     /// instructions in the range between the two iterators.
291     ///
292     /// Currently, the only only changes that are supported are simple removal
293     /// and addition of uses.
294     void repairIntervalsInRange(MachineBasicBlock *MBB,
295                                 MachineBasicBlock::iterator Begin,
296                                 MachineBasicBlock::iterator End,
297                                 ArrayRef<unsigned> OrigRegs);
298 
299     // Register mask functions.
300     //
301     // Machine instructions may use a register mask operand to indicate that a
302     // large number of registers are clobbered by the instruction.  This is
303     // typically used for calls.
304     //
305     // For compile time performance reasons, these clobbers are not recorded in
306     // the live intervals for individual physical registers.  Instead,
307     // LiveIntervalAnalysis maintains a sorted list of instructions with
308     // register mask operands.
309 
310     /// getRegMaskSlots - Returns a sorted array of slot indices of all
311     /// instructions with register mask operands.
getRegMaskSlots()312     ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
313 
314     /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
315     /// instructions with register mask operands in the basic block numbered
316     /// MBBNum.
getRegMaskSlotsInBlock(unsigned MBBNum)317     ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
318       std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
319       return getRegMaskSlots().slice(P.first, P.second);
320     }
321 
322     /// getRegMaskBits() - Returns an array of register mask pointers
323     /// corresponding to getRegMaskSlots().
getRegMaskBits()324     ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
325 
326     /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
327     /// to getRegMaskSlotsInBlock(MBBNum).
getRegMaskBitsInBlock(unsigned MBBNum)328     ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
329       std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
330       return getRegMaskBits().slice(P.first, P.second);
331     }
332 
333     /// checkRegMaskInterference - Test if LI is live across any register mask
334     /// instructions, and compute a bit mask of physical registers that are not
335     /// clobbered by any of them.
336     ///
337     /// Returns false if LI doesn't cross any register mask instructions. In
338     /// that case, the bit vector is not filled in.
339     bool checkRegMaskInterference(LiveInterval &LI,
340                                   BitVector &UsableRegs);
341 
342     // Register unit functions.
343     //
344     // Fixed interference occurs when MachineInstrs use physregs directly
345     // instead of virtual registers. This typically happens when passing
346     // arguments to a function call, or when instructions require operands in
347     // fixed registers.
348     //
349     // Each physreg has one or more register units, see MCRegisterInfo. We
350     // track liveness per register unit to handle aliasing registers more
351     // efficiently.
352 
353     /// getRegUnit - Return the live range for Unit.
354     /// It will be computed if it doesn't exist.
getRegUnit(unsigned Unit)355     LiveInterval &getRegUnit(unsigned Unit) {
356       LiveInterval *LI = RegUnitIntervals[Unit];
357       if (!LI) {
358         // Compute missing ranges on demand.
359         RegUnitIntervals[Unit] = LI = new LiveInterval(Unit, HUGE_VALF);
360         computeRegUnitInterval(LI);
361       }
362       return *LI;
363     }
364 
365     /// getCachedRegUnit - Return the live range for Unit if it has already
366     /// been computed, or NULL if it hasn't been computed yet.
getCachedRegUnit(unsigned Unit)367     LiveInterval *getCachedRegUnit(unsigned Unit) {
368       return RegUnitIntervals[Unit];
369     }
370 
getCachedRegUnit(unsigned Unit)371     const LiveInterval *getCachedRegUnit(unsigned Unit) const {
372       return RegUnitIntervals[Unit];
373     }
374 
375   private:
376     /// Compute live intervals for all virtual registers.
377     void computeVirtRegs();
378 
379     /// Compute RegMaskSlots and RegMaskBits.
380     void computeRegMasks();
381 
382     static LiveInterval* createInterval(unsigned Reg);
383 
384     void printInstrs(raw_ostream &O) const;
385     void dumpInstrs() const;
386 
387     void computeLiveInRegUnits();
388     void computeRegUnitInterval(LiveInterval*);
389     void computeVirtRegInterval(LiveInterval*);
390 
391     class HMEditor;
392   };
393 } // End llvm namespace
394 
395 #endif
396